Semiconductor memory device and method for producing the same
View Patent ↗Disclosed is a non-volatile semiconductor memory device that uses a inversion layer provided on a semiconductor substrate as a data line. The memory device can reduce variation of characteristics among memory cells and can reduce bit cost. A plurality of assist gates are formed in the upper part of a p-type well through a gate oxide film. In the upper part of an interlayer insulator that covers those assist gates are formed word lines that are used as control electrodes. The width of those word lines is, for example, 0.1 μm, and each word line is separated from its adjacent word lines by a side wall spacer that is a silicon oxide film having a thickness of about 20 nm.
1. A semiconductor memory device, comprising:
a memory cell array having first memory cells, second memory cells, third memory cells and fourth memory cells;
a first word line (W 0 ), extending to a first direction, connected to the first memory cells;
a second word line (W 1 ), extending to the first direction, connected to the second memory cells and being adjacent to the first word line;
a third word line (W 2 ), extending to the first direction, connected to the third memory cells and being adjacent to the second word line;
a fourth word line (W 3 ), extending to the first direction, connected to the fourth memory cells and being adjacent to the third word line;
a first contact region where the first contact and the second contact are disposed;
a second contact region where the third contact and the fourth contact are disposed;
a first contact connected the first word line in the first contact region;
a second contact connected the second word line in the first contact region;
a third contact connected to the third word line in the second contact region;
and a fourth contact connected to the fourth word line in the second contact region;
wherein the memory cell array is disposed between the first contact region and the second contact region,
wherein a distance from the first contact to the memory cell array in the first direction is different from that from the second contact to the memory cell array in the first direction, and wherein a distance from the third contact to the memory cell array in the first direction is different from that from the third contact to the memory cell array in the first direction.
2. A semiconductor memory device according to claim 1 ,
wherein the distance from the first contact to the memory cell array in the first direction is shorter than that from the second contact to the memory cell array in the first direction, and
wherein the distance from the third contact to the memory cell array in the first direction is shorter than that from the third contact to the memory cell array in the first direction.
3. A semiconductor memory device according to claim 1 ,
wherein the first contact and the second contact are not disposed on one line extending to a second direction, being perpendicular to the first direction, and
wherein the third contact and the fourth contact are not disposed on the other line extending to the second direction.
4. A semiconductor memory device according to claim 1 ,
wherein a width in a second direction, being perpendicular to the first direction, between the first word line and the second word line is less than that of the first word line,
wherein a width in the second direction between the second word line and the third word line is less than that of the second word line, and
wherein a width in the second direction between the third word line and the fourth word line is less than that of the third word line.
5. A semiconductor memory device according to claim 1 ,
wherein the memory cell array has a plurality of unit comprising the first, second, third and fourth word lines.
6. A semiconductor memory device according to claim 1 ,
wherein the second word line has a fist contact pad in the first contact region and the second contact is disposed on the first contact pad, and
wherein the fourth word line has a second contact pad in the second contact region and the fourth contact is disposed on the second contact pad.
7. A semiconductor memory device according to claim 6 ,
wherein the first contact pad is disposed such that a part of the first contact pad is arranged on the extending line of the first word line, and
wherein the second contact pad is disposed such that a part of the second contact pad is arranged on the extending line of the third word line.