Semiconductor device including a SRAM section and a logic circuit section
View Patent ↗A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.
1. A semiconductor device including a SRAM section and a logic circuit section, comprising:
a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and
a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section,
wherein a first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.
2. The semiconductor device of claim 1 , further comprising:
a first p-type MIS transistor including a first p-type gate electrode formed with a third gate insulating film interposed on a third element formation region of the semiconductor substrate in the SRAM section; and
a first element isolation region formed between the first element formation region and the third element formation region of the semiconductor substrate,
wherein the first n-type gate electrode is integrally formed with the first p-type gate electrode.
3. The semiconductor device of claim 2 ,
wherein a third impurity concentration of a p-type impurity in the first p-type gate electrode is lower than the first impurity concentration.
4. The semiconductor device of claim 2 ,
wherein a pn boundary between the first n-type gate electrode and the first p-type gate electrode is located at a point on the first element isolation region.
5. The semiconductor device of claim 2 , further comprising:
a second p-type MIS transistor including a second p-type gate electrode formed with a fourth gate insulting film interposed on a fourth element formation region of the semiconductor substrate in the logic circuit section; and
a second element isolation region formed between the second element formation region and the fourth element formation region of the semiconductor substrate,
wherein the second n-type gate electrode is formed integrally with the second p-type gate electrode.
6. The semiconductor device of claim 5 ,
wherein a pn boundary between the second n-type gate electrode and the second p-type gate electrode is located at a point on the second element isolation region.
7. The semiconductor device of claim 5 ,
wherein the first element isolation region has a width in a gate width direction smaller than the second element isolation region.
8. The semiconductor device of claim 1 ,
wherein the first n-type gate electrode has a width in a gate width direction smaller than the second n-type gate electrode.
9. The semiconductor device of claim 1 ,
wherein the first gate insulating film and the second gate insulating film are formed of a same insulting film.
10. The semiconductor device of claim 1 ,
wherein the first n-type gate electrode and the second n-type gate electrode are polysilicon electrodes.