Semiconductor device
View Patent ↗The semiconductor device includes: an A/D conversion circuit for A/D-converting an analog input signal and outputting a resultant conversion result; and a computation circuit for performing, in synchronization with the A/D conversion circuit, computation for an updated conversion result without storing the updated conversion result every time the conversion result from the A/D conversion circuit is updated, to determine one computation result from a plurality of conversion results from the A/D conversion circuit and output the computation result.
1. A semiconductor device comprising:
an A/D conversion circuit for A/D-converting an analog input signal and outputting a resultant conversion result; and
a computation circuit for performing, in synchronization with the A/D conversion circuit, computation for an updated conversion result without storing the updated conversion result every time the conversion result from the A/D conversion circuit is updated, to determine one computation result from a plurality of conversion results from the A/D conversion circuit and output the computation result.
2. The semiconductor device of claim 1 , wherein the computation circuit determines the computation result from a plurality of conversion results outputted from the A/D conversion circuit when the voltage of the analog input signal is constant.
3. The semiconductor device of claim 1 , further comprising:
a digital processing circuit for performing predetermined processing using the conversion result from the A/D conversion circuit and outputting the processing result; and
a selector for selecting an output of the digital processing circuit or an output of the computation circuit and outputting the selected one.
4. The semiconductor device of claim 1 , wherein the computation circuit determines an average value of a plurality of conversion results from the A/D conversion circuit as the computation result.
5. The semiconductor device of claim 4 , wherein the computation circuit determines a sum of the n-th (n is a natural number) power of 2 conversion results from the A/D conversion circuit and outputs a portion of the summed result other than the n least significant bit or bits as the computation result.
6. The semiconductor device of claim 1 , wherein the computation circuit determines a sum of a plurality of conversion results from the A/D conversion circuit as the computation result.
7. The semiconductor device of claim 1 , wherein the computation circuit determines any of a plurality of conversion results from the A/D conversion circuit as the computation result.
8. The semiconductor device of claim 7 , wherein the computation circuit determines any of conversion results, among a plurality of conversion results from the A/D conversion circuit, other than one conversion result whose value is maximum and one conversion result whose value is minimum, as the computation result.
9. The semiconductor device of claim 7 , wherein the computation circuit determines a conversion result located in the middle among a plurality of conversion results from the A/D conversion circuit when they are sorted in descending order, as the computation result.
10. The semiconductor device of claim 7 , wherein the computation circuit comprises:
an initial value memory for storing a first conversion result from the A/D conversion circuit;
a subtractor for determining a difference of a second or subsequent conversion result from the value in the initial value memory;
a counter section having a counter corresponding to every value the difference can take on;
a difference value distribution circuit for incrementing the value of a counter corresponding to the value of a difference determined by the subtractor every time the subtractor determines a difference;
a difference detection circuit for determining the value of a difference located in the middle among differences determined from the second and subsequent conversion results from the A/D conversion circuit when they are sorted in descending order, based on the values of the counters; and
an adder for adding the value determined by the difference detection circuit to the value in the initial value memory and outputting the added result.
11. A semiconductor device comprising:
a signal generator for generating an analog input signal and outputting the generated signal;
a computation circuit for performing, in synchronization with an A/D conversion circuit for A/D-converting the analog input signal and outputting the converted signal, computation for an updated conversion result without storing the updated conversion result every time the conversion result from the A/D conversion circuit is updated, to determine one computation result from a plurality of conversion results from the A/D conversion circuit and output the computation result; and
a signal reader for analyzing the computation result.
12. The semiconductor device of claim 11 , wherein the signal generator generates an analog input signal having a constant voltage, and
the computation circuit determines the computation result from a plurality of conversion results outputted from the A/D conversion circuit when the voltage of the analog input signal is constant.
13. The semiconductor device of claim 11 , wherein the computation circuit determines an average value of a plurality of conversion results from the A/D conversion circuit as the computation result.
14. The semiconductor device of claim 13 , wherein the computation circuit determines a sum of the n-th (n is a natural number) power of 2 conversion results from the A/D conversion circuit and outputs a portion of the summed result other than the n least significant bit or bits as the computation result.
15. The semiconductor device of claim 11 , wherein the computation circuit determines a sum of a plurality of conversion results from the A/D conversion circuit as the computation result.
16. The semiconductor device of claim 11 , wherein the computation circuit determines any of a plurality of conversion results from the A/D conversion circuit as the computation result.
17. The semiconductor device of claim 16 , wherein the computation circuit determines any of conversion results, among a plurality of conversion results from the A/D conversion circuit, other than one conversion result whose value is maximum and one conversion result whose value is minimum, as the computation result.
18. The semiconductor device of claim 16 , wherein the computation circuit determines a conversion result located in the middle among a plurality of conversion results from the A/D conversion circuit when they are sorted in descending order, as the computation result.
19. The semiconductor device of claim 16 , wherein the computation circuit comprises:
an initial value memory for storing a first conversion result from the A/D conversion circuit;
a subtractor for determining a difference of a second or subsequent conversion result from the value in the initial value memory;
a counter section having a counter corresponding to every value the difference can take on;
a difference value distribution circuit for incrementing the value of a counter corresponding to the value of a difference determined by the subtractor every time the subtractor determines a difference;
a difference detection circuit for determining the value of a difference located in the middle among differences determined from the second and subsequent conversion results from the A/D conversion circuit when they are sorted in descending order, based on the values of the counters; and
an adder for adding the value determined by the difference detection circuit to the value in the initial value memory and outputting the added result.