Semiconductor device with reduced parasitic inductance
View Patent ↗The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETS, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.
1. A semiconductor device comprising:
a conductive first chip mounting portion having a first main surface and a second main surface on an opposite side thereof;
a first external terminal for supplying input power disposed near the first chip mounting portion;
a second external terminal for supplying a reference potential disposed near the first chip mounting portion;
a third external terminal integrally formed with the first chip mounting portion for providing an output;
a first semiconductor chip mounted on the first main surface of the first chip mounting portion;
a second semiconductor chip mounted on the first main surface of the first chip mounting portion;
a first plate conductive component which electrically connects an electrode of the second semiconductor chip to the second external terminal;
a second plate conductive component which electrically connects an electrode of the first semiconductor chip to the first external terminal;
a second chip mounting portion having a first main surface and a second main surface on an opposite side thereof;
a third semiconductor chip mounted on the first main surface of the second chip mounting portion;
an n-channel vertical field effect transistor formed on the first semiconductor chip and the second semiconductor chip;
a bonding wire which connects source electrode pads and gate electrode pads of the third semiconductor chip and the first semiconductor chip;
a bonding wire which connects source electrodes and gate electrodes of the third semiconductor chip and the second semiconductor chip; and
a sealing body which seals the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, the first plate conductive component, the second plate conductive component, and the bonding wires,
wherein the source electrode of the first semiconductor chip and a drain electrode of the second semiconductor chip are electrically connected to the first chip mounting portion, and
wherein one electrode of a capacitor is electrically connected via a first connection layer to the first plate conductive component, and the other electrode of the capacitor is electrically connected via a second connection layer to the second plate conductive component.
2. A power source unit of a synchronous rectification type, in which a DC input power source and one main terminal of a rectification MOSFET are connected to a positive potential side of the DC input power source, the other main terminal is connected to one main terminal of a choke coil and one main terminal of a commutation MOSFET, the other main terminal of the commutation MOSFET is connected to a negative potential side of the DC input power source, one terminal of an output capacitor is connected to the other terminal of the choke coil, the other terminal of the output capacitor is connected to the other main terminal of the commutation MOSFET, one terminal which supplies electric power to a semiconductor device to be a load is connected to the other terminal of the choke coil, the other terminal which supplies electric power to the semiconductor device to be a load is connected to the other main terminal of the commutation MOSFET, and gates of the rectification MOSFET and the commutation MOSFET are driven by a control circuit, wherein the power source unit is coupled to the semiconductor device of claim 1 as follows:
the positive potential side of the DC input power source is coupled to the first external terminal of the semiconductor device,
the negative potential side of the DC input power source is coupled to the second external terminal of the semiconductor device, and
the choke coil is coupled to the third external terminal of the semiconductor device.