Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave
View Patent ↗Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave. A means is presented by which any desired number of parallel implemented turbo decoding processors can be employed to perform turbo decoding that has been performed using a QPP interleave. This approach is presented to allow an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) to perform decoding of a turbo coded signal while still using a selected embodiment of a QPP interleave. In addition, a collision-free memory mapping, MOD,C,W ) provides more freedom for selecting the particular quadratic polynomial permutation (QPP) interleave (π) that satisfies a parallel turbo decoding implementation with any desired number of parallel implemented turbo decoding processors. This memory mapping allows collision-free reading and writing of updated information (as updated using parallel implemented turbo decoder) into memory banks.
1. A turbo decoder for performing parallel decoding of a turbo coded signal generated using a quadratic polynomial permutation (QPP) interleave, the turbo decoder comprising:
a plurality of turbo decoders including any integer number of turbo decoders between 2 and an information block length of the turbo coded signal; and
a plurality of memories; and wherein:
during a first decoding cycle:
each turbo decoder of the plurality of turbo decoders retrieving first information from a first respective, corresponding memory of the plurality of memories as directed by a first mapping of a collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories; and
each turbo decoder of the plurality of turbo decoders performing decoding processing using the first information retrieved from its first respective, corresponding memory of the plurality of memories thereby generating first updated information; and
the first updated information written over the first information in each first corresponding memory of the plurality of memories;
during a second decoding cycle:
each turbo decoder of the plurality of turbo decoders retrieving second information from a second respective, corresponding memory of the plurality of memories as directed by a second mapping of the collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories; and
each turbo decoder of the plurality of turbo decoders performing decoding processing using the information retrieved from its second respective, corresponding memory of the plurality of memories thereby generating second updated information; and
the second updated information written over the second information in each first corresponding memory of the plurality of memories; and
the plurality of turbo decoders generating a best estimate of at least one bit that has been encoded into the turbo coded signal.
2. The turbo decoder of claim 1 , further comprising:
a processing module for performing collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories during iterative decoding processing of the turbo coded signal; and wherein:
the processing module providing the first mapping of the collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories;
the processing module providing the second mapping of the collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories; and
the collision-free modulation memory mapping associating the plurality of turbo decoders and the plurality of memories is determined based on at least one of the information block length of the turbo coded signal and a virtual block length of the turbo coded signal.
3. The turbo decoder of claim 1 , wherein:
when performing turbo decoding, a turbo decoder of the plurality of turbo decoders performing QPP interleaving on extrinsic information thereby generating “a priori probability” (app) information for use in subsequent decoding processing.
4. The turbo decoder of claim 1 , wherein:
when performing turbo decoding, a turbo decoder of the plurality of turbo decoders performing QPP de-interleaving on extrinsic information thereby generating “a priori probability” (app) information for use in subsequent decoding processing.
5. The turbo decoder of claim 1 , wherein a turbo decoder of the plurality of turbo decoders including:
a first soft-in/soft-out (SISO) decoder for:
receiving a plurality of metrics associated with the turbo coded signal; and
performing SISO decoding on the plurality of metrics thereby calculating first extrinsic information;
an interleaver module for performing interleaving on the first extrinsic information thereby generating first “a priori probability” (app) information; and
a second SISO decoder for performing SISO decoding on the first app information thereby generating second extrinsic information;
a de-interleaver module for performing de-interleaving on the second extrinsic information thereby generating second app information; and
an output processor for processing most recent extrinsic information that has been generated by the second SISO decoder thereby generating best estimates of information bits encoded within the turbo coded signal.
6. The turbo decoder of claim 1 , wherein a turbo decoder of the plurality of turbo decoders including:
a first soft-in/soft-out (SISO) decoder for:
receiving a plurality of metrics associated with a the turbo coded signal; and
performing SISO decoding on the plurality of metrics thereby calculating first extrinsic information;
an interleaver module for performing QPP interleaving on the first extrinsic information thereby generating first “a priori probability” (app) information;
a second SISO decoder for performing SISO decoding on the first app information thereby generating second extrinsic information;
a de-interleaver module for performing QPP de-interleaving on the second extrinsic information thereby generating second app information; and
an output processor for processing most recent extrinsic information that has been generated by the second SISO decoder thereby generating best estimates of information bits encoded within the turbo coded signal.
7. The turbo decoder of claim 1 , wherein:
the plurality of turbo decoders including a number of turbo decoders; and
the plurality of memories including the number of memories.
8. The turbo decoder of claim 1 , wherein:
the plurality of turbo decoders including a first number of turbo decoders; and
the plurality of memories including a second number of memories.
9. The turbo decoder of claim 1 , wherein:
the turbo decoder being implemented within a wireless personal communication device.
10. The turbo decoder of claim 1 , wherein:
the turbo decoder being implemented within a communication device; and
the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
11. A turbo decoder for performing parallel decoding of a turbo coded signal generated using a quadratic polynomial permutation (QPP) interleave, the turbo decoder comprising:
a plurality of turbo decoders including any integer number of turbo decoders between 2 and an information block length of the turbo coded signal;
a plurality of memories; and
a processing module for performing collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories during iterative decoding processing of the turbo coded signal; and wherein:
during a first decoding cycle:
each turbo decoder of the plurality of turbo decoders retrieving first information from a first respective, corresponding memory of the plurality of memories as directed by a first mapping of a collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories; and
each turbo decoder of the plurality of turbo decoders performing decoding processing using the first information retrieved from its first corresponding memory of the plurality of memories thereby generating first updated information;
the first updated information written over the first information in each first corresponding memory of the plurality of memories; and
the processing module providing the first mapping of the collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories;
during a second decoding cycle:
each turbo decoder of the plurality of turbo decoders retrieving second information from a second respective, corresponding memory of the plurality of memories as directed by a second mapping of the collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories; and
each turbo decoder of the plurality of turbo decoders performing decoding processing using the information retrieved from its second respective, corresponding memory of the plurality of memories thereby generating second updated information;
the second updated information written over the second information in each first corresponding memory of the plurality of memories; and
the processing module providing the second mapping of the collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories; and
the plurality of turbo decoders generating a best estimate of at least one bit that has been encoded into the turbo coded signal; and
when performing turbo decoding, a turbo decoder of the plurality of turbo decoders performing:
QPP interleaving on first extrinsic information thereby generating first “a priori probability” (app) information for use in subsequent decoding processing; and
QPP de-interleaving on second extrinsic information thereby generating second “a priori probability” (app) information for use in subsequent decoding processing.
12. The turbo decoder of claim 11 , wherein a turbo decoder of the plurality of turbo decoders including:
a first soft-in/soft-out (SISO) decoder for:
receiving a plurality of metrics associated with the turbo coded signal; and
performing SISO decoding on the plurality of metrics thereby calculating first extrinsic information;
an interleaver module for performing QPP interleaving on the first extrinsic information thereby generating first “a priori probability” (app) information;
a second SISO decoder for performing SISO decoding on the first app information thereby generating second extrinsic information;
a de-interleaver module for performing QPP de-interleaving on the second extrinsic information thereby generating second app information; and
an output processor for processing most recent extrinsic information that has been generated by the second SISO decoder thereby generating best estimates of information bits encoded within the turbo coded signal.
13. The turbo decoder of claim 11 , wherein:
the plurality of turbo decoders including a number of turbo decoders; and
the plurality of memories including the number of memories.
14. The turbo decoder of claim 11 , wherein:
the turbo decoder being implemented within a wireless personal communication device.
15. The turbo decoder of claim 11 , wherein:
the turbo decoder being implemented within a communication device; and
the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
16. A turbo decoder for performing parallel decoding of a turbo coded signal generated using a quadratic polynomial permutation (QPP) interleave, the turbo decoder comprising:
a plurality of turbo decoders including any integer number of turbo decoders between 2 and an information block length of the turbo coded signal; and
a plurality of memories; and wherein:
during a first decoding cycle:
each turbo decoder of the plurality of turbo decoders retrieving first information from a first respective, corresponding memory of the plurality of memories as directed by a first mapping of a collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories; and
each turbo decoder of the plurality of turbo decoders performing decoding processing using the first information retrieved from its first respective, corresponding memory of the plurality of memories thereby generating first updated information; and
the first updated information written over the first information in each first corresponding memory of the plurality of memories;
during a second decoding cycle:
each turbo decoder of the plurality of turbo decoders retrieving second information from a second respective, corresponding memory of the plurality of memories as directed by a second mapping of the collision-free modulation memory mapping between the plurality of turbo decoders and the plurality of memories; and
each turbo decoder of the plurality of turbo decoders performing decoding processing using the information retrieved from its second respective, corresponding memory of the plurality of memories thereby generating second updated information; and
the second updated information written over the second information in each first corresponding memory of the plurality of memories; and
the plurality of turbo decoders generating a best estimate of at least one bit that has been encoded into the turbo coded signal;
each turbo decoder of the plurality of turbo decoders respectively including:
a first soft-in/soft-out (SISO) decoder for:
receiving a plurality of metrics associated with the turbo coded signal; and
performing SISO decoding on the plurality of metrics thereby calculating first extrinsic information;
an interleaver module for performing interleaving on the first extrinsic information thereby generating first “a priori probability” (app) information; and
a second SISO decoder for performing SISO decoding on the first app information thereby generating second extrinsic information;
a de-interleaver module for performing de-interleaving on the second extrinsic information thereby generating second app information; and
an output processor for processing most recent extrinsic information that has been generated by the second SISO decoder thereby generating best estimates of information bits encoded within the turbo coded signal.
17. The turbo decoder of claim 16 , wherein:
the plurality of turbo decoders including a number of turbo decoders; and
the plurality of memories including the number of memories.
18. The turbo decoder of claim 16 , wherein:
the plurality of turbo decoders including a first number of turbo decoders; and
the plurality of memories including a second number of memories.
19. The turbo decoder of claim 16 , wherein:
the turbo decoder being implemented within a wireless personal communication device.
20. The turbo decoder of claim 16 , wherein:
the turbo decoder being implemented within a communication device; and
the communication device being operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.