Software accessible cache metadata
Various technologies and techniques are disclosed for providing software accessible metadata on a cache of a central processing unit. The metadata can include at least some bits for each virtual address, at least some bits for each cache line, and at least some bits for the cache overall. An instruction set architecture on the central processing unit is provided that includes additional instructions for interacting with the metadata. New side effects that are introduced into an operation of the central processing unit by a presence of the metadata and the additional instructions. The metadata can be accessed by at least one software program to facilitate an operation of the software program.
1. A computer system comprising:
a central processing unit configured to execute a plurality of different software application programs, the central processing unit having:
a plurality of logical processors;
a cache comprising a plurality of cache lines, wherein a respective cache line of the plurality of cache lines is augmented by a plurality of cache metadata per respective logical processor of the plurality of logical processors, and stores a plurality of cached data blocks, and wherein the plurality of cache metadata includes both cache line metadata that provides state information about the respective cache line and virtual address metadata that provides state information about a respective cached data block of the plurality of cached data blocks; and
an instruction set architecture associated with the central processing unit that provides instructions that may be executed by any of the plurality of different software application programs to access the cache line metadata and the virtual address metadata to facilitate the performance of an operation.
2. The system of claim 1 , wherein the central processing unit further comprises cache metadata control registers that configure operation of and indicate status of the plurality of cache metadata.
3. The system of claim 2 , wherein the cache metadata control registers include at least one default value register.
4. The system of claim 1 , wherein the respective cache line of the plurality of cache lines is associated with one or more bits of the plurality of cache metadata.
5. The system of claim 4 , wherein the plurality of cached data blocks in the cache are associated with one or more bits of the plurality of cache metadata.
6. The system of claim 1 , wherein the cache is shared by a plurality of cores in the central processing unit.
7. The system of claim 1 , wherein the cache is shared by a plurality of hardware thread contexts in a single central processing unit.
8. The system of claim 1 , wherein automatic hardware cache operations interact with the plurality of cache metadata.
9. The system of claim 8 , wherein upon a cache line load operation, at least some cache metadata of the plurality of cache metadata are initialized from default values.
10. The system of claim 9 , wherein default values are specified by cache metadata control registers.
11. The system of claim 8 , wherein upon line eviction or invalidation, a cache line metadata eviction summary register is compared with a cache line metadata evictions handler mask register and execution is selectively directed to a software program specified by an evictions handler address register.
12. The system of claim 8 , wherein upon line eviction or invalidation, a cache line metadata eviction summary register is updated to reflect a corresponding cache line metadata of a particular line being evicted or invalidated.
13. A computer system comprising:
a central processing unit configured to execute a plurality of different software application programs, the central processing unit including a plurality of logical processors and a cache that contains cache metadata, per respective logical processor of the plurality of logical processors, that are accessible by any of the different software application programs to improve an operation of any of the different software application programs, the cache metadata including both cache line metadata that provides state information about an associated one of a plurality of cache lines stored in the cache and virtual address metadata that provides state information about an associated one of a plurality of cached data blocks in a respective cache line of the plurality of cache lines; and
an instruction set architecture on the central processing unit that includes a set of instructions that enable any of the different software application programs to access both the cache line metadata and the virtual address metadata.
14. The system of claim 13 , wherein the set of instructions further include instructions that enable any of the different software application programs to read the cache metadata.
15. The system of claim 14 , wherein the set of instructions include instructions that enable any of the different software application programs to update the cache metadata.
16. The system of claim 13 , wherein the set of instructions include instructions that enable any of the different software application programs to perform logical operations on the cache metadata.
17. The system of claim 13 , wherein the instruction set architecture contains automatic cache and processor operations that interact with at least some of the cache metadata.
18. The system of claim 17 , wherein the instruction set architecture contains instructions for interacting with cache metadata control registers.
19. The system of claim 18 , wherein the instruction set architecture contains instructions for operating on memory locations conditional on the contents of one or more pieces of the cache metadata.
20. A computer system comprising:
a central processing unit configured to execute a plurality of different software application programs, the central processing unit including:
a plurality of logical processors;
a cache comprising a plurality of cache lines, wherein a respective cache line of the plurality of cache lines is augmented by a plurality of cache metadata per respective logical processor of the plurality of logical processors, the plurality of cache metadata comprising virtual address metadata bits associated with respective cached data blocks of a plurality of cached data blocks included in the respective cache line and cache line metadata bits associated with the respective cache line;
an instruction set architecture on the central processing unit that includes instructions that may be executed by any of the different software application programs to enable any of the different software application programs to interact with the virtual address metadata bits and the cache line metadata bits; and
hardware operation behaviors that are introduced into the operation of the central processing unit and cache by presence of the cache metadata and the instructions that enable any of the different software application programs to interact with the virtual address metadata bits and the cache line metadata bits.