Polysilicon thin film transistor device with gate electrode thinner than gate line
View Patent ↗A polysilicon thin film transistor device includes a gate metal pattern including a gate electrode and a gate line formed on a substrate, the gate metal pattern having a stepped portion, a gate insulating film formed on the gate metal pattern, a polysilicon semiconductor layer formed on the gate insulating film, the polysilicon semiconductor layer including an active region, lightly doped drain regions, a source region, and a drain region, a source electrode connected to the source region and a drain electrode connected to the drain region on the polysilicon semiconductor layer, and a pixel electrode connected with the drain electrode.
1. A polysilicon thin film transistor device, comprising:
a buffer layer formed on a substrate;
a gate metal pattern including a gate electrode and a gate line formed on the buffer layer;
a gate insulating film formed on the gate metal pattern;
a polysilicon semiconductor layer formed on the gate insulating film, the polysilicon semiconductor layer including an active region, lightly doped drain regions, a source region and a drain region;
a source electrode connected to the source region and a drain electrode connected to the drain region on the polysilicon semiconductor layer; and
a pixel electrode connected with the pixel electrode,
wherein the gate metal pattern is a single layer of a metal material, and the thickness of the gate electrode is less than the thickness of the gate line.