Semiconductor device with back surface electrode including a stress relaxation film
View Patent ↗A semiconductor device includes a semiconductor substrate which has first and second principal surface regions; an insulated gate structure which is formed in the first principal surface region; a back surface region semiconductor layer which is formed in the second principal surface region and has a thickness of at most 5 μm; an outermost metal film; and a back surface electrode which is formed in the second principal surface region between the back surface region semiconductor layer and the outermost metal film and which is composed of a plurality of films which are laminated and include a stress relaxation film so that false judgment of chip quality based on leakage current measurements during manufacturing is reduced particularly when dust is present and skews leakage current measurements due to strain on the wafer and the piezoelectric effect produced.
1. A semiconductor device, comprising:
a semiconductor substrate having first and second principal surface regions;
an insulated gate structure which is formed in the first principal surface region;
a back surface region semiconductor layer which is formed in the second principal surface region and has a thickness of at most 5 μm;
an outermost metal film; and
a back surface electrode which is formed in the second principal surface region between the back surface region semiconductor layer and the outermost metal film and which is composed of a plurality of films which are laminated and include a stress relaxation film.
2. The semiconductor device according to claim 1 , wherein the back surface region semiconductor layer is one of a back surface region diffusion layer or a back surface region epitaxial layer.
3. The semiconductor device according to claim 2 , wherein the stress relaxation film is a conductive film exhibiting a ductility which is large.
4. The semiconductor device according to claim 3 , wherein the conductive film is an Al—Si film containing silicon in an amount of at most 2 wt %.
5. The semiconductor device according to claim 2 , wherein the plurality of films which compose the back surface electrode include one of (a) an Al—Si film, a metal barrier film, and a nickel film, or (b) a titanium film, an Al—Si film, a metal barrier film, and a nickel film and are sequentially formed in this order from the back surface region semiconductor layer towards the outermost metal film.
6. The semiconductor device according to claim 5 , wherein the metal barrier film is selected from the group consisting of a titanium film, a molybdenum film, and a tungsten film.
7. The semiconductor device according to claim 2 , wherein the semiconductor device is an FS-IGBT and the back surface region semiconductor layer is composed of a field stop layer and a collector layer that is formed in contact with the field stop layer.
8. The semiconductor device according to claim 2 , wherein the semiconductor is a diode and the back surface region semiconductor layer is a cathode layer.
9. The semiconductor device according to claim 2 , wherein the semiconductor is a MOSFET and the back surface region semiconductor layer is a drain layer.
10. The semiconductor device according to claim 2 , further comprising a depletion layer which extends in the semiconductor substrate and which reaches the back surface region semiconductor layer at a rated voltage applied between the first principal surface and the second principal surface.
11. The semiconductor device according to claim 1 , wherein the stress relaxation film is a conductive film exhibiting a ductility which is large.
12. The semiconductor device according to claim 11 , wherein the conductive film is an Al—Si film containing silicon in an amount of at most 2 wt %.
13. The semiconductor device according to claim 1 , wherein the plurality of films which compose the back surface electrode include one of (a) an Al—Si film, a metal barrier film, and a nickel film, or (b) a titanium film, an Al—Si film, a metal barrier film, and a nickel film and are sequentially formed in this order from the back surface region semiconductor layer towards the outermost metal film.
14. The semiconductor device according to claim 13 , wherein the metal barrier film is selected from the group consisting of a titanium film, a molybdenum film, and a tungsten film.
15. The semiconductor device according to claim 1 , wherein the semiconductor device is an FS-IGBT and the back surface region semiconductor layer is composed of a field stop layer and a collector layer that is formed in contact with the field stop layer.
16. The semiconductor device according to claim 1 , wherein the semiconductor is a diode and the back surface region semiconductor layer is a cathode layer.
17. The semiconductor device according to claim 1 , wherein the semiconductor is a MOSFET and the back surface region semiconductor layer is a drain layer.
18. The semiconductor device according to claim 1 , further comprising a depletion layer which extends in the semiconductor substrate and which reaches the back surface region semiconductor layer at a rated voltage applied between the first principal surface and the second principal surface.
19. A semiconductor device, comprising:
an n semiconductor substrate having first and second principal surface regions;
an insulated gate structure formed in the first principal surface region;
a back surface region diffusion layer formed in the second principal surface region, having a thickness of at most 5 μm, and being comprised of:
an n field stop layer formed in the back surface region and having a surface region, and
a p collector layer formed on the surface region of the n field stop layer;
an outermost metal film; and
a back surface electrode formed in the second principal surface region of the semiconductor substrate between the back surface region semiconductor layer and the outermost metal film and composed of a plurality of films which are laminated and which include at least one titanium film, a nickel film, and a stress relaxation film provided so that rate of false judgment of leakage current due to a piezoelectric effect is reduced.
20. The semiconductor device according to claim 19 , wherein the stress relaxation film is conductive and ductile, and wherein the stress relaxation film is an Al—Si film having a thickness ranging from about 0.3 μm to about 4 μm.