Analogue/digital converter device
View Patent ↗In a scanning mode: a conversion sequence setting register sets the sequence in which analogue signals are to be converted; a multiplexer selects a single analogue signal sequentially from a plurality of analogue signals, in accordance with the order that is set in this conversion sequence setting register; an A/D converter converts the analogue signal selected by this multiplexer to a digital signal; a conversion result register having a plurality of result registers stores the digital signal obtained by conversion by the A/D converter in these storage regions in the order in which conversion was effected; and a back-up register includes result registers respectively corresponding to this plurality of result registers.
1. An analogue/digital conversion device comprising:
a conversion sequence setting register in which an order analogue signals are converted when in a scanning mode during which a plurality of analogue signals are consecutively converted to digital signals is set;
a multiplexer that selects sequentially a single analogue signal from said plurality of analogue signals, in an order that is set in said conversion sequence setting register;
an analogue/digital converter that converts an analogue signal that is selected by said multiplexer to a digital signal and operable in the scanning mode for continuous A/D conversion of a plurality of input signals in a fixed order, and a select mode for individual A/D conversion of any desired input signal with any desired timing; and
a conversion result register having a plurality of storage regions, that stores a digital signal obtained as a result of a conversion by said analogue/digital converter in storage regions in an order with which conversion was effected.
2. The analogue/digital conversion device according to claim 1 ,
further comprising a stop decision unit that stops conversion by said analogue/digital converter when a predetermined number is selected in accordance with the order that is set in said conversion sequence setting register.
3. The analogue/digital conversion device according to claim 1 or claim 2 ,
further comprising a command register that is constituted such that an instruction for starting of conversion by said analogue/digital converter can be received by means of a start signal passing through a bus under the control of a processor, or a start signal from another peripheral device.
4. An analogue/digital conversion device comprising:
a multiplexer that selects a single analogue signal from a plurality of analogue signals in accordance with a first selection signal;
an analogue/digital converter that converts said analogue signal that is selected by said multiplexer to a digital signal;
a conversion result register having a plurality of storage regions, that stores a digital signal obtained as a result of a conversion by said analogue/digital converter in a corresponding storage region in accordance with a second selection signal;
a conversion channel setting register wherein a selection signal of an analogue signal to be converted is set, during a select mode in which a single analogue signal is selected and converted to a digital signal;
a conversion sequence setting register in which an order of analogue signals to be converted is set, during a scanning mode, in which a plurality of analogue signals are consecutively converted to digital signals;
a counter that counts number of times conversion is effected in scanning mode;
a structural unit that provides a continuous scanning mode whereby, after conversion is completed corresponding to number of times conversion is performed in one cycle in scanning mode, said scanning mode conversion cycle is again repeated, in accordance with the order that is set in said conversion sequence setting register;
a first selector whereby, in the case of a select mode, a selection signal that is set in said conversion channel setting register is supplied to said multiplexer as said first selection signal and, in the case of a scanning mode, said order that is output from said conversion sequence setting register specified by a count value of said counter is supplied to said multiplexer as said first selection signal; and
a second selector whereby, in the case of a select mode, a selection signal that is set in said conversion channel setting register is supplied to said conversion result register as said second selection signal and, in the case of a scanning mode, a count value of said counter is supplied to said conversion result register as said second selection signal.
5. The analogue/digital conversion device according to claim 4 ,
further comprising a stop decision unit that stops conversion by said analogue/digital converter when said order that is output from said conversion sequence setting register has reached a predetermined number in the case of said scanning mode.
6. The analogue/digital conversion device according to claim 5 ,
further comprising a back-up register having a plurality of storage regions in which data of said conversion result register that stores said digital signal converted by said analogue/digital converter is saved,
wherein data of said conversion result register is saved by said back-up register with a timing with which a conversion cycle is again commenced after conversion is completed corresponding to number of times conversion is performed in one cycle in said continuous scanning mode.
7. The analogue/digital conversion device according to claim 4 or claim 5 ,
further comprising a command register that is constituted such that an instruction for starting of conversion by said analogue/digital converter can be received by means of a start signal passing through a bus under the control of a processor, or a start signal from another peripheral device.
8. The analogue/digital conversion device according to claim 1 or claim 4 ,
further comprising a back-up register having a plurality of storage regions in which data of said conversion result register that stores the digital signal converted by said analogue/digital converter is saved,
wherein data of said conversion result register is saved by said back-up register with a timing with which said start-up signal obtained through said bus under the control of said processor or a start-up signal from another peripheral device is input from said command register to give instructions for start-up of conversion.
9. The analogue/digital conversion device according to claim 4 ,
further comprising a back-up register having a plurality of storage regions in which data of said conversion result register that stores said digital signal converted by said analogue/digital converter is saved,
wherein data of said conversion result register is saved by said back-up register with a timing with which a conversion cycle is again commenced after conversion is completed corresponding to number of times conversion is performed in one cycle in said continuous scanning mode.