METHOD AND APPARATUS FOR TUNING A DIGITAL SYSTEM
A digital system 1 comprises receiving means ( 5 ) for receiving one or more performance indicators or parameters from software ( 6 ) controlling the execution of an application ( 3 ). Based on the performance indicators received by the receiving means ( 5 ), a tuning circuit ( 7 ) is provided for tuning the frequency (f), supply voltage (Vdd) and/or the transistor threshold voltage (Vb) of the digital system ( 1 ). In addition, pipeline configuration means ( 8 ) are provided for configuring the pipeline of the digital system ( 1 ) based on a pipeline depth determined by selecting means ( 10 ). The selecting means ( 10 ) is configured to select the pipeline depth (Pd) based on the frequency (f), supply voltage (Vdd), transistor threshold voltage (Vb), and according to whether the application requires maximum throughput or minimum latency.
1 . A method of tuning the performance of a digital system, the method comprising the steps of: receiving one or more performance indicators relating to the performance of the digital system;—tuning the frequency, supply voltage and/or transistor threshold voltage of the digital system to obtain a desired performance; and thereafter adjusting the pipeline depth of the digital system to fine tune the performance of the digital system.
2 . A method as claimed in claim 1 , wherein prior to the step of adjusting the pipeline depth there is the step of determining an optimum pipeline depth for a given frequency.
3 . A method as claimed in claim 2 , wherein the step of determining the optimum pipeline depth is based on achieving maximum throughput in the digital system.
4 . A method as claimed in claim 2 , wherein the step of determining the optimum pipeline depth is based on achieving the minimum latency in the digital system.
5 . A method as claimed in claim 2 , wherein the step of determining the optimum pipeline depth is based on achieving a compromise between throughput and latency in the digital system.
6 . A method as claimed in claim 1 , wherein the step of adjusting the pipeline depth comprises the step of skipping one or more register banks separating different pipeline stages in the digital system.
7 . A method as claimed in claim 1 , wherein different parts of the digital system are tuned according to different performance indicators.
8 . A method as claimed in claim 1 , wherein the digital system is an IP block or SoC.
9 . Apparatus for tuning the performance of a digital system, the apparatus comprising: means for receiving one or more performance indicators relating to the performance of the digital system; tuning means for tuning the frequency, supply voltage and/or transistor threshold voltage of the digital system to obtain a desired performance; and pipeline configuration means for adjusting the pipeline depth of the digital system after the tuning means has tuned the digital system, thereby fine tuning the performance of the digital system.
10 . Apparatus as claimed in claim 9 , further comprising selecting means for selecting an optimum pipeline depth for obtaining the desired performance.
11 . Apparatus as claimed in claim 10 , wherein the selecting means is configured to select an optimum pipeline depth for achieving maximum throughput in the digital system.
12 . Apparatus as claimed in claim 10 , wherein the selecting means is configured to select an optimum pipeline depth for achieving minimum latency in the digital system.
13 . Apparatus as claimed in claim 10 , wherein the selecting means is configured to select an optimum pipeline depth for achieving a compromise between throughput and latency in the digital system.
14 . Apparatus as claimed in claim 9 , wherein the pipeline configuration means for adjusting the pipeline depth comprises means for skipping one or more register banks separating different pipeline stages in the digital system.
15 . Apparatus as claimed in claim 9 , wherein different parts of the digital system are configured to be tuned according to different performance indicators.
16 . Apparatus as claimed in claim 9 , wherein the digital system is an IP block or SoC.