IP Library Granted Patent US 7,933,373
Granted Patent B2
US 7,933,373 · App. 11/814,602 · Granted Apr 26, 2011

Phase correction circuit of encoder signal

Assignee: Panasonic Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,933,373
App. No.
11/814,602
Granted
Apr 26, 2011
Kind
B2
Abstract

A position detector has a peak detector for detecting peak values of an A 1 signal and a B 1 signal serving as output signals of an analog to digital (AD) converter, an offset/amplitude correction section for generating an A 2 signal and a B 2 signal by correcting offsets and amplitude errors using the peak values detected by the peak detector, and a position data conversion section for converting the sinusoidal signals of an A phase and a B phase into position data.

Claims (20)

1. A phase correction circuit of an encoder signal in a position detector, the position detector having:

an analog to digital (AD) converter for generating an A 1 signal and a B 1 signal by converting sinusoidal signals of an A phase and a B phase having a phase difference of 90 degrees into digital data;

a peak detector for detecting peak values of the A 1 signal and the B 1 signal;

an offset/amplitude correction section for generating an A 2 signal and a B 2 signal by correcting offsets and an amplitude error using the peak values detected by the peak detector; and

a position data conversion section for converting the sinusoidal signals of the A phase and the B phase into position data, the phase correction circuit comprising:

a phase error detector for detecting an intersection value of the A 2 signal and the B 2 signal; and

a phase correction section for computing a correction factor of the A 2 signal and the B 2 signal from the intersection value detected by the phase error detector,

wherein the phase correction section generates an A correction signal and a B correction signal by multiplying the A 2 signal and the B 2 signal by the correction factor and corrects phase errors of the A phase and the B phase by adding the B correction signal to the A 2 signal and adding the A correction signal to the B 2 signal.

2. The phase correction circuit of an encoder signal of claim 1 , wherein the phase error detector detects a value of the B 2 signal at a point at which the phase error detector detects the peak value of the A 1 signal, and detects a value of the A 2 signal at a point at which the peak value of the B 1 signal is detected.

3. The phase correction circuit of an encoder signal of claim 1 , wherein the phase correction section obtains the correction factor computed based on the intersection value of the A 2 signal and the B 2 signal and a sign-inverted correction factor computed by the phase error detector based on a sign-inverted signal of the A 2 signal or the B 2 signal and an intersection value of the B 2 signal or the A 2 signal, and averages and uses the two correction factors.

4. The phase correction circuit of an encoder signal of claim 2 , wherein the phase correction section computes the correction factor by detecting a value of the B 2 signal or the A 2 signal at a point at which the phase error detector detects a maximum value of the A 2 signal or the B 2 signal, computes an sign-inverted correction factor by detecting a value of the B 2 signal or the A 2 signal at a point at which a minimum value of the A 2 signal or the B 2 signal is detected, and averages and uses the computed correction factors.

5. The phase correction circuit of an encoder signal of claim 1 , wherein the phase correction section computes the correction factor by detecting phase lead and lag from the intersection value of the A 2 signal or the B 2 signal and detecting a value of the B 2 signal or the A 2 signal at a point at which the phase error detector detects an intersection point with zero of the A 2 signal or the B 2 signal.

6. The phase correction circuit of an encoder signal of claim 2 , wherein the phase correction section computes the correction factor by detecting phase lead and lag from a value of the B 2 signal or the A 2 signal at a point at which a maximum value or a minimum value of the A 2 signal or the B 2 signal is detected and detecting a value of the B 2 signal or the A 2 signal at a point at which the phase error detector detects an intersection point with zero of the A 2 signal or the B 2 signal.

7. The phase correction circuit of an encoder signal of claim 1 , wherein an amplitude correction factor is computed from a phase error detected by the phase error detector and an amplitude of the sinusoidal signals of the A phase and the B phase corrected by the phase correction section is corrected.

8. The phase correction circuit of an encoder signal of claim 2 , wherein an amplitude correction factor is computed from a phase error detected by the phase error detector and an amplitude of the sinusoidal signals of the A phase and the B phase corrected by the phase correction section is corrected.

9. The phase correction circuit of an encoder signal of claim 3 , wherein an amplitude correction factor is computed from a phase error detected by the phase error detector and an amplitude of the sinusoidal signals of the A phase and the B phase corrected by the phase correction section is corrected.

10. The phase correction circuit of an encoder signal of claim 4 , wherein an amplitude correction factor is computed from a phase error detected by the phase error detector and an amplitude of the sinusoidal signals of the A phase and the B phase corrected by the phase correction section is corrected.

11. The phase correction circuit of an encoder signal of claim 5 , wherein an amplitude correction factor is computed from a phase error detected by the phase error detector and an amplitude of the sinusoidal signals of the A phase and the B phase corrected by the phase correction section is corrected.

12. The phase correction circuit of an encoder signal of claim 6 , wherein an amplitude correction factor is computed from a phase error detected by the phase error detector and an amplitude of the sinusoidal signals of the A phase and the B phase corrected by the phase correction section is corrected.

13. The phase correction circuit of claim 1 , wherein the phase correction section corrects the phase errors of the A phase and the B phase simultaneously.

Assignments (2)
CHANGE OF NAME Recorded Nov 11, 2008
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 021818/0725 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2008
From: KISHIBE, TARO; MASUDA, TAKAHIRO; TANOUE, HIROMI
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 020348/0084 →
Priority Claims (1)
JP 2006-168327 · Jun 19, 2006 · national
Continuity (1)
Related Publication 20100091926A1 · Apr 15, 2010