Allocating registers for loop variables in a multi-threaded processor
View Patent ↗A multi-threaded processor comprises a processing unit (PU) for concurrently processing multiple threads. A register file means (RF) is provided having a plurality of registers, wherein a first register (LI) is used for storing loop invariant values and N second registers (LVI-LVN) are each used for storing loop variant values. Furthermore N program counters (PCI-PCN) are provided each being associated to one of the multiple threads, wherein N being the number of threads being processed.
1. A method, comprising:
identifying one or more loop invariant values and one or more loop variant values of a loop to be executed by a multi-threaded processor having a register file shared by a plurality of threads, wherein the one or more loop invariant values are to be accessed by the multi-threaded processor within the loop;
allocating a first register set from the register file to provide the plurality of threads with shared access to the one or more loop invariant values of the loop; and
allocating a plurality of second register sets from the register file to the plurality of threads, wherein ones of the plurality of second register sets are configured to provide a different thread of the plurality of threads with non-shared access to the one or more loop variant values of the loop.
2. The method of claim 1 , wherein:
said identifying comprises determining a quantity of loop invariant values for the loop; and
said allocating a first register set comprises assigning a quantity of registers to the first register set equal to the quantity of loop invariant values for the loop.
3. The method of claim 1 , wherein:
said identifying comprises determining the loop has a single loop invariant value; and
said allocating a first register set comprises assigning a single register of the register file to the first register set.
4. The method of claim 1 , wherein:
said identifying comprises determining the loop has a plurality of the loop invariant values; and
said allocating a first register set comprises assigning a plurality of registers of the register file to the first register set.
5. The method of claim 1 , wherein:
said identifying comprises determining a quantity of loop variant values for the loop; and
said allocating a plurality of second register sets comprises assigning to each second register set a quantity of registers equal to the quantity of loop variant values for the loop.
6. The method of claim 1 , wherein:
said identifying comprises determining the loop has a single loop variant value; and
said allocating a plurality of second register sets comprises assigning a separate, single register of the register file to each second register set.
7. The method of claim 1 , wherein:
said identifying comprises determining the loop has a plurality of loop variant values; and
said allocating a plurality of second register sets comprises assigning a separate, plurality of registers of the register file to each second register set.
8. A multi-threaded processor, comprising:
a processing unit configured to execute a plurality of threads;
a program counter configured to store a separate address for ones of the plurality of threads; and
a register file comprising a plurality of registers, wherein the register file comprises a first register set and a plurality of second register sets, wherein the register file is configured to provide the plurality of threads with shared access to one or more loop invariant values of a loop via the first register set, and to provide threads included in the plurality of threads with non-shared access to one or more loop variant values of the loop via a separate second register set associated with the thread included in the plurality of threads;
wherein the one or more loop invariant values are to be accessed by the plurality of threads within the loop.
9. The multi-threaded processor of claim 8 , wherein the register files is further configured to assign a quantity of registers to the first register set equal to a quantity of loop invariant values for the loop.
10. The multi-threaded processor of claim 8 , wherein the register file is further configured to assign a single register of the register file to the first register set.
11. The multi-threaded processor of claim 8 , wherein the register file is further configured to assign a plurality of registers of the register file to the first register set.
12. The multi-threaded processor of claim 8 , wherein the register file is further configured to assign to each second register set a quantity of registers equal to a quantity of loop variant values for the loop.
13. The multi-threaded processor of claim 8 , wherein the register file is further configured to assign a separate, single register of the register file to each second register set.
14. The multi-threaded processor of claim 8 , wherein the register file is further configured to assign a separate, plurality of registers of the register file to each second register set.
15. A method, comprising:
reading, with a computing device, a first set of instructions that defines a loop for a multi-threaded processor having a register file shared by a plurality of threads;
identifying one or more loop invariant values and one or more loop variant values of the loop, wherein the one or more loop invariant values are to be accessed within the loop; and
generating, with the computing device, a second set of instructions, that in response to being executed by the multi-threaded processor, cause the multi-threaded processor to allocate a first register set and a plurality of second registers sets from the register file to the plurality of threads, store one or more loop invariant values of the loop in the first register set, and store one or more loop variant values of the loop in the plurality of second register sets;
wherein the second set of instructions further configures the first register set to provide the plurality of threads with shared access to the one or more loop invariant values of the loop, and further configures ones of the second register set to provide a separate thread of the plurality of threads with non-shared access to the one or more loop variant values of the loop.
16. The method of claim 15 , wherein said generating a second set of instructions further comprises generating the second set of instructions such that the second set of instructions further cause the multi-threaded processor to assign a quantity of registers to the first register set equal to a quantity of loop invariant values for the loop.
17. The method of claim 15 , wherein said generating a second set of instructions further comprises generating the second set of instructions such that the second set of instructions further cause the multi-threaded processor to assign a single register of the register file to the first register set.
18. The method of claim 15 , wherein said generating a second set of instructions further comprises generating the second set of instructions such that the second set of instructions further cause the multi-threaded processor to assign a plurality of registers of the register file to the first register set.
19. The method of claim 15 , wherein said generating a second set of instructions further comprises generating the second set of instructions such that the second set of instructions further cause the multi-threaded processor to assign to each second register set a quantity of registers equal to a quantity of loop variant values for the loop.
20. The method of claim 15 , wherein said generating a second set of instructions further comprises generating the second set of instructions such that the second set of instructions further cause the multi-threaded processor to assign a separate, single register of the register file to each second register set.
21. The method of claim 15 , wherein said generating a second set of instructions further comprises generating the second set of instructions such that the second set of instructions further cause the multi-threaded processor to assign a separate, plurality of registers of the register file to each second register set.