IP Library Granted Patent US 9,146,865
Granted Patent B2
US 9,146,865 · App. 11/814,914 · Granted Sep 29, 2015

Operating a dual-ported internal memory

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Quick Facts
Patent No.
US 9,146,865
App. No.
11/814,914
Granted
Sep 29, 2015
Kind
B2
Abstract

There is provided a method for updating an internal memory on a semiconductor device from an external memory. The external memory is arranged in a plurality of data portions. The method comprises the steps of writing a first data portion from the external memory to the internal memory, processing the first data portion and, while the first data portion is being processed, once a selected data item is processed, starting to write a second data portion from the external memory to the internal memory. The method may be applied to the processing of software by an embedded processor on a semiconductor device. There is also provided a semiconductor device and a hardware module for the semiconductor device.

Claims (33)

1. A method for updating a dual ported internal memory on a semiconductor chip from an external memory, wherein the external memory is external to the semiconductor chip, and wherein the external memory comprises a data file, the method comprising:

writing a first data portion of the data file from the external memory to the dual ported internal memory by a memory controller;

processing the first data portion in the dual ported internal memory by a processor, wherein the dual ported internal memory, the processor and the memory controller are on the semiconductor chip; and

while the first data portion is being processed, once a selected data item is processed, starting to write a second data portion of the data file from the external memory to the dual ported internal memory,

wherein writing the first data portion from the external memory to the dual ported internal memory comprises:

reading an external data address defined by x bits for each data item in the first data portion;

discarding y bits from the external data address thereby writing an internal data address having (x-y) bits; and

wherein processing the first data portion comprises reading, for each data item, the internal data address having (x-y) bits,

wherein the selected data item is defined by one or more of the internal data addresses in the set, and wherein the one or more of the internal data addresses defining the selected data item is set by a user.

2. A semiconductor chip for operation with an external memory, the external memory being external to the semiconductor chip, the semiconductor chip comprising:

a dual ported internal memory for storing a data portion;

a memory controller for writing data from the external memo to the dual ported internal memory;

a processor for processing the data portion in the dual ported internal memory; and

a hardware module arranged, once a selected data item in a first data portion is processed, to instruct the memory controller to write a second data portion from the external memory to the dual ported internal memory, wherein the external memory comprises a data file and wherein the data file is arranged in a plurality of data portions,

wherein each data portion in the external memory is defined by a set of external data addresses,

wherein data in the dual ported internal memory is defined by a set of internal data addresses,

wherein each set of external data addresses is substantially the same size as the set of internal data addresses,

wherein each external data address is defined by x bits and each internal data address is defined by (x-y) bits, and

wherein the processor is arranged, when processing the data portion in the dual ported internal memory, to try to read, for each data item in the first data portion, an address defined by x bits, and the dual ported internal memory is arranged to convert the address defined by x bits to an internal memory address defined by (x-y) bits, by discarding the y most significant bits of the data address,

wherein the selected data item is defined by one or more of the internal data addresses in the set and wherein the one or more of the internal data addresses defining the selected data item can be set by a user.

3. A system comprising:

a first chip comprising an external memory, wherein the external memory comprises a data file and wherein the data file is arranged in a plurality of data portions; and

a second chip comprising

a dual ported memory for storing one data portion;

a memory controller configured to write a first data portion from the external memory to the dual ported memory;

a processor configured to process the first data portion in the dual ported memory; and

a hardware module configured to instruct the memory controller to write a second data portion from the external memory to the dual ported memory once a selected data item in a first data portion is processed,

wherein each data portion in the external memory is defined by a set of memory data addresses,

wherein data in the dual ported memory is defined by a set of dual ported data addresses,

wherein each set of memory data addresses is substantially the same size as the set of dual ported data addresses,

wherein each memory data address is defined by x bits and each dual ported data address is defined by (x-y) bits, and

wherein the processor is arranged, when processing the first data portion in the dual ported memory, to read, for each data item in the first data portion, an address defined by x bits, and the dual ported memory is arranged to convert the address defined by x bits to an dual ported data address defined by (x-y) bits, by discarding the y most significant bits of the data address,

wherein the selected data item is defined by one or more of the dual ported data addresses and wherein the one or more of the dual ported data addresses defining the selected data item is set by a user.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2020
From: LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: INTEL CORPORATION
Reel/Frame 053259/0678 →
MERGER AND CHANGE OF NAME Recorded Jan 17, 2018
From: LANTIQ DEUTSCHLAND GMBH; LANTIQ BETEILIGUNGS-GMBH & CO. KG
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 045085/0292 →
MERGER Recorded Dec 18, 2017
From: LANTIQ DEUTSCHLAND GMBH
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 044907/0045 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 025413/0340 AND 025406/0677 Recorded Apr 17, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LANTIQ BETEILIGUNGS-GMBH & CO. KG
Reel/Frame 035453/0712 →
GRANT OF SECURITY INTEREST IN U.S. PATENTS Recorded Nov 29, 2010
From: LANTIQ DEUTSCHLAND GMBH
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 025406/0677 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2010
From: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
To: LANTIQ DEUTSCHLAND GMBH
Reel/Frame 024529/0614 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2010
From: INFINEON TECHNOLOGIES AG
To: INFINEON TECHNOLOGIES WIRELESS SOLUTIONS GMBH
Reel/Frame 024474/0937 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2007
From: KAMIKO, TARO; LEE, YAO CHYE; NAYAK, GANESHA; SOW, JIN SZE
To: INFINEON TECHNOLOGIES AG
Reel/Frame 019756/0436 →