Thin film transistor array panel with overlapping floating electrodes and pixel electrodes
View Patent ↗According to an embodiment of the present invention, a thin film transistor array panel includes a gate line and a data line insulated from each other on an insulating substrate where the gate line and the data line cross each other to define a pixel region, a thin film transistor (TFT) disposed at an intersection of the gate line and the data line, a floating electrode where at least a portion of the floating electrode overlaps the data line, and a pixel electrode disposed at the pixel region where the pixel electrode is connected to the TFT and overlaps the at least a portion of the floating electrode.
1. A thin film transistor (TFT) array panel, comprising:
at least one gate line and at least one data line insulated from each other on an insulating substrate;
at least two pixel electrodes;
at least one thin film transistor (TFT) including a gate electrode, a source electrode and a drain electrode respectively, wherein the gate electrode is connected to the gate line, the source electrode is connected to the data line, and the drain electrode is connected to one of the pixel electrodes; and
a capacitive electrode, at least a portion of the capacitive electrode overlapping the data line, wherein the capacitive electrode overlaps the pixel electrodes, and the capacitive electrode is without an opening or a slit facing the data line; and
an ohmic contact layer disposed between the data line and the capacitive electrode, wherein a width of the ohmic contact layer is larger than a width of the data line;
wherein one of the pixel electrodes is disposed in a first pixel region and another one of the pixel electrodes is disposed in a second pixel region.
2. The TFT array panel of claim 1 , wherein the capacitive electrode is disposed parallel to the data line so that the at least a portion of the capacitive electrode overlaps the data line.
3. The TFT array panel of claim 1 , wherein the capacitive electrode is disposed on the same layer as the gate line.
4. The TFT array panel of claim 1 , wherein the pixel electrode overlaps an immediately preceding second gate line adjacent to the gate line to form a storage capacitor.
5. The TFT array panel of claim 4 , wherein the capacitive electrode partially overlaps at least one side of each of the pixel electrodes.
6. The TFT array panel of claim 4 , wherein the capacitive electrode is formed into a polygonal structure.
7. The TFT array panel of claim 4 , wherein the capacitive electrode is disposed vertically between the gate lines.
8. The TFT array panel of claim 1 , wherein at least a portion of the pixel electrode overlaps a separate storage electrode to form a storage capacitor.
9. The TFT array panel of claim 8 , wherein the pixel electrode is disposed over the capacitive electrode to at least partially overlap the capacitive electrode at one side of the data line.
10. The TFT array panel of claim 8 , wherein the pixel electrode is disposed over the capacitive electrode to at least partially overlap the floating electrode at both sides of the data line.
11. The TFT array panel of claim 8 , wherein the capacitive electrode is formed into a polygonal structure.
12. The TFT array panel of claim 8 , wherein the capacitive electrode includes first and second electrodes with the data line interposed therebetween, the first and second electrodes being connected to each other by a coupling electrode that is at least partially overlapping the data line.
13. The TFT array panel of claim 1 , wherein a width of an overlap between the capacitive electrode and a first pixel electrode is substantially equal to a width of an overlap between the capacitive electrode and a second pixel electrode adjacent to the first pixel electrode.
14. The TFT array panel of claim 1 , wherein the capacitive electrode is divided into first and second portions which do not overlap the data line, and wherein the first and second portions are generally symmetric with respect to the data line.