Amplitude modulation driver

1. A circuit comprising:

an amplitude modulation path coupled to a first input of a power amplifier;

a first semiconductor device coupled to sink current flowing through the amplitude modulation path, the first semiconductor device comprising a first source region, a first gate region, and a first drain region, the first gate region and the first drain region separated by a first distance; and

a second semiconductor device comprising a second source region, a second gate region, and a second drain region, the second gate region and the second drain region separated by a second distance;

wherein the first distance is greater than the second distance and the first semiconductor device is coupled to the second semiconductor device.

2. The circuit of claim 1 , wherein the first semiconductor device comprises a larger voltage drop than the second semiconductor device.

3. The circuit of claim 1 , wherein the first semiconductor device comprises an increased tolerance to voltage fluctuations.

4. The circuit of claim 1 , wherein the first gate region comprises a polycrystalline silicon material.

5. The circuit of claim 1 , wherein the first semiconductor device comprises an NMOS type semiconductor device.

6. A circuit comprising:

a first semiconductor device comprising a first source region, a first gate region, and a first drain region, the first gate region and the first drain region separated by a first distance;

a second semiconductor device comprising a second source region, a second gate region, and a second drain region, the second gate region and the second drain region separated by a second distance, wherein the first distance is greater than the second distance;

an input voltage line;

a drain lead of the first semiconductor device coupled to the input voltage line;

a source lead of the first semiconductor device coupled to a drain lead of the second semiconductor device; and

a drain lead of the second semiconductor device coupled to a low voltage,

such that the first semiconductor device and the second semiconductor device are stacked.

7. A circuit comprising:

a first semiconductor device comprising a first source region, a first gate region, and a first drain region, the first gate region and the first drain region separated by a first distance;

a second semiconductor device comprising a second source region, a second gate region, and a second drain region, the second gate region and the second drain region separated by a second distance, wherein the first distance is greater than the second distance and the first semiconductor device is coupled to the second semiconductor device;

a signal input;

a third semiconductor device;

a gate lead of the third semiconductor device coupled to the signal input, and

a fourth semiconductor device coupling the first, second, and third semiconductor devices to a power amplifier, the power amplifier for outputting a modulated signal.

8. A polar modulator comprising:

a power amplifier for outputting a modulated signal;

an envelope modulator coupled to a first input of the power amplifier;

an amplitude modulator coupled to the envelope modulator, the amplitude modulator and the envelope modulator forming an amplitude modulation path;

a first semiconductor device coupled to sink current flowing through the amplitude modulation path, the first semiconductor device comprising a first source region, a first gate region, and a first drain region, the first gate region and the first drain region separated by a first distance; and

a second semiconductor device coupled to first semiconductor device as a switch to deactivate a signal path in the first semiconductor device, the second semiconductor device comprising a second source region, a second gate region, and a second drain region, the second gate region and the second drain region separated by a second distance;

wherein the first distance is greater than the second distance and the first semiconductor device is coupled to the second semiconductor device.

9. The polar modulator of claim 8 , wherein the polar modulator is coupled to a transceiver circuit, the transceiver circuit for selectively transmitting and receiving a message signal.

10. The polar modulator of claim 9 , the transceiver circuit further comprising a set of polar coordinates.

11. The polar modulator of claim 8 , wherein the first semiconductor device comprises a larger voltage drop than the second semiconductor device.

12. The polar modulator of claim 8 , wherein the first semiconductor device comprises an increased tolerance to voltage fluctuations.

13. The polar modulator of claim 8 , wherein the first gate region comprises a polycrystalline silicon material.

14. The polar modulator of claim 8 , wherein the first semiconductor device comprises an NMOS type semiconductor device.

15. The polar modulator of claim 8 , further comprising:

an input power line;

a drain lead of the first semiconductor device coupled to the input power line;

a source lead of the first semiconductor device coupled to a drain lead of the second semiconductor device, and

a drain lead of the second semiconductor device coupled to a low voltage,

such that the first semiconductor device and the second semiconductor device are in a stacked configuration.

16. The polar modulator of claim 8 , further comprising:

a signal input;

a third semiconductor device, a gate lead of the third semiconductor device coupled to the signal input within the signal path; and

a fourth semiconductor device coupling the first, second, and third semiconductor devices to a power amplifier, the power amplifier for outputting a modulated signal, wherein the first semiconductor device is coupled to the fourth semiconductor device to sink current flowing through the fourth semiconductor device.

17. An amplitude modulation driver comprising:

an envelope modulator coupled to a first input of the power amplifier;

an amplitude modulator coupled to the envelope modulator the amplitude modulator and the envelope modulator forming an amplitude modulation path;

a first semiconductor device coupled to sink current flowing through the amplitude modulation path, the first semiconductor device comprising a first source region, a first gate region, and a first drain region, the first gate region and the first drain region separated by a first distance;

a second semiconductor device comprising a second source region, a second gate region, and a second drain region, the second gate region and the second drain region separated by a second distance;

wherein the first distance is greater than the second distance and the first semiconductor device is coupled to the second semiconductor device.

18. The amplitude modulation driver of claim 17 , wherein the first semiconductor device and the second semiconductor device are within a radio frequency integrated circuit (RFIC), wherein a gate lead of the second semiconductor device is coupled to a switching voltage.