Non-volatile memory with source/drains in multiple directions
View Patent ↗An object is to improve a data recording amount per memory cell. In the invention, in a non-volatile memory, the data contents of which can be electrically written and erased, each memory cell that configures the non-volatile memory is provided with: source/drain regions formed on a semiconductor substrate; a gate electrode formed on a channel region of the semiconductor substrate; and a gate insulating film formed between the semiconductor substrate and the gate electrode. A configuration in which the source/drain regions extend at least in three directions from the channel region when seen on a plane from the gate electrode side is employed.
1. A non-volatile memory fabricated on a semiconductor substrate, into and from which data can be electrically written and erased, each memory cell of said memory comprising:
an active region formed on the semiconductor substrate;
at least one source region formed on the active region;
at least one drain region formed on the active region, a portion of the active region between the source and drain regions being a channel region;
a gate electrode formed on the channel region, the gate electrode extending from the channel region in first two directions in a plan view; and
a gate insulating film formed on the channel region and beneath the gate electrode, wherein
both said source and drain regions extend in at least three directions from said channel region in the plan view, and every one of said source and drain regions extends from the channel region in a direction different from the first two directions in the plan view.
2. The non-volatile memory according to claim 1 , wherein said gate insulating film includes first and second insulating film layers and a dielectric layer formed between the insulating film layers.
3. The non-volatile memory according to claim 2 , wherein said first insulating film layer and said second insulating film layer are made from silicon oxide films and said dielectric layer is made from a silicon nitride film.
4. The non-volatile memory according to claim 1 , wherein said source and drain regions are formed with two strip-shaped diffusion regions that intersect with each other on said gate electrode formed in a strip shape in the plan view.
5. The non-volatile memory according to claim 2 , wherein said source and drain regions are formed with two strip-shaped diffusion regions that intersect with each other on said gate electrode formed in a strip shape in the plan view.
6. The non-volatile memory according to claim 3 , wherein said source and drain regions are formed with two strip-shaped diffusion regions that intersect with each other on said gate electrode formed in a strip shape in the plan view.
7. The non-volatile memory according to claim 1 , wherein said source and drain regions are formed with three strip-shaped diffusion regions that intersect with each other on said gate electrode formed in a strip shape in the plan view.
8. The non-volatile memory according to claim 2 , wherein said source and drain regions are formed with three strip-shaped diffusion regions that intersect with each other on said gate electrode formed in a strip shape in the plan view.
9. The non-volatile memory according to claim 3 , wherein said source and drain regions are formed with three strip-shaped diffusion regions that intersect with each other on said gate electrode formed in a strip shape in the plan view.