Semiconductor device and method for fabricating the same
View Patent ↗The distance between a substrate contact portion and an active region in a p-type MIS transistor is greater than the distance between a substrate contact portion and an active region in an n-type MIS transistor. Alternatively, the length of a protruding part of a gate electrode of the p-type MIS transistor that protrudes from the p-type MIS transistor's active region toward the p-type MIS transistor's substrate contact portion is shorter than the length of a protruding part of a gate electrode of the n-type MIS transistor that protrudes from the n-type MIS transistor's active region toward the n-type MIS transistor's substrate contact portion. Alternatively, a part of the p-type MIS transistor's substrate contact portion that is located opposite the p-type MIS transistor's gate electrode has a lower impurity concentration than the other part thereof. Alternatively, a protective film is formed only on the protruding part of the p-type MIS transistor's gate electrode that protrudes from the p-type MIS transistor's active region toward the p-type MIS transistor's substrate contact portion.
1. A semiconductor device having a dual-gate structure, the device comprising:
a first active region of an n-type MIS transistor and a second active region of a p-type MIS transistor formed on a semiconductor substrate so as to be adjacent to each other with a first isolation region interposed therebetween;
a first substrate contact portion of the n-type MIS transistor formed on the semiconductor substrate near the first active region;
a second substrate contact portion of the p-type MIS transistor formed on the semiconductor substrate near the second active region;
an n-type gate electrode formed over the first active region and containing an n-type impurity introduced thereinto;
a first p-type doped layer formed in the first substrate contact portion and containing a p-type impurity introduced thereinto;
a p-type gate electrode formed over the second active region and containing a p-type impurity introduced thereinto;
a first n-type doped layer formed in the second substrate contact portion and containing an n-type impurity introduced thereinto;
a second p-type doped layer formed in a protruding part of the n-type gate electrode, where the n-type gate electrode protrudes from the first active region toward the first substrate contact portion and containing a p-type impurity introduced thereinto; and
a second n-type doped layer formed in a protruding part of the p-type gate electrode, where the p-type gate electrode protrudes from the second active region toward the second substrate contact portion and containing a n-type impurity introduced thereinto,
wherein the first active region and the first substrate contact portion are separated by a second isolation region located between the first active region and the first substrate contact portion,
the second active region and the second substrate contact portion are separated by a third isolation region located between the second active region and the second substrate contact portion,
a distance between the second substrate contact portion and the second active region is greater than a distance between the first substrate contact portion and the first active region, and
a width of the second n-type doped layer in the gate width direction is smaller than a width of the second p-type doped layer in the gate width direction.
2. The semiconductor device of claim 1 , wherein
the length of the protruding part of the n-type gate electrode in the gate width direction that protrudes from the first active region toward the first substrate contact portion on the second isolation region is set equal to the length of the protruding part of the p-type gate electrode in the gate width direction that protrudes from the second active region toward the second substrate contact portion on the third isolation region.
3. The semiconductor device of claim 1 , wherein
a distance between the first substrate contact portion and the n-type gate electrode is shorter than a distance between the second substrate contact portion and the p-type gate electrode.
4. The semiconductor device of claim 1 , wherein
a width of the first active region in the gate length direction is smaller than a width of the first substrate contact portion in the gate length direction, and
a width of the second active region in the gate length direction is smaller than a width of the second substrate contact portion in the gate length direction.
5. The semiconductor device of claim 1 , further comprising:
a first insulating sidewall spacer formed on a sidewall of the n-type gate electrode located near the first substrate contact portion; and
a second insulating sidewall spacer formed on a sidewall of the p-type gate electrode located near the second substrate contact portion, wherein
the first insulating sidewall spacer is extended in the direction from the second isolation region to the first substrate contact portion, and
the second insulating sidewall spacer is not formed on the second substrate contact portion, and is formed only on the third isolation region.
6. A semiconductor device having a dual-gate structure, the device comprising:
a first active region of an n-type MIS transistor and a second active region of a p-type MIS transistor formed on a semiconductor substrate so as to be adjacent to each other with a first isolation region interposed therebetween;
a first substrate contact portion of the n-type MIS transistor formed on the semiconductor substrate near the first active region;
a second substrate contact portion of the p-type MIS transistor formed on the semiconductor substrate near the second active region;
an n-type gate electrode formed over the first active region and containing an n-type impurity introduced thereinto;
a p-type doped layer formed in the first substrate contact portion and containing a p-type impurity introduced thereinto;
a p-type gate electrode formed over the second active region and containing a p-type impurity introduced thereinto;
an n-type doped layer formed in the second substrate contact portion and containing an n-type impurity introduced thereinto;
a second p-type doped layer formed in a protruding part of the n-type gate electrode, where the n-type gate electrode protrudes from the first active region toward the first substrate contact portion and containing a p-type impurity introduced thereinto; and
a second n-type doped layer formed in a protruding part of the p-type gate electrode, where the p-type gate electrode protrudes from the second active region toward the second substrate contact portion and containing a n-type impurity introduced thereinto,
wherein the first active region and the first substrate contact portion are separated by a second isolation region located between the first active region and the first substrate contact portion,
the second active region and the second substrate contact portion are separated by a third isolation region located between the second active region and the second substrate contact portion,
the length of a protruding part of the p-type gate electrode in the gate width direction that protrudes from the second active region toward the second substrate contact portion on the third isolation region is shorter than the length of a protruding part of the n-type gate electrode in the gate width direction that protrudes from the first active region toward the first substrate contact portion on the second isolation region, and
a width of the second n-type doped layer in the gate width direction is smaller than a width of the second p-type doped layer in the gate width direction.
7. The semiconductor device of claim 6 , wherein the distance between the second substrate contact portion and the second active region is set equal to the distance between the first substrate contact portion and the first active region.
8. The semiconductor device of claim 6 , wherein
a distance between the first substrate contact portion and the n-type gate electrode is shorter than a distance between the second substrate contact portion and the p-type gate electrode.
9. The semiconductor device of claim 6 , wherein
a width of the first active region in the gate length direction is smaller than a width of the first substrate contact portion in the gate length direction, and
a width of the second active region in the gate length direction is smaller than a width of the second substrate contact portion in the gate length direction.
10. The semiconductor device of claim 6 , further comprising:
a first insulating sidewall spacer formed on a sidewall of the n-type gate electrode located near the first substrate contact portion; and
a second insulating sidewall spacer formed on a sidewall of the p-type gate electrode located near the second substrate contact portion, wherein
the first insulating sidewall spacer is extended in the direction from the second isolation region to the first substrate contact portion, and
the second insulating sidewall spacer is not formed on the second substrate contact portion, and is formed only on the third isolation region.
11. A semiconductor device having a dual-gate structure, the device comprising:
a first active region of an n-type MIS transistor and a second active region of a p-type MIS transistor formed on a semiconductor substrate so as to be adjacent to each other with a first isolation region interposed therebetween;
a first substrate contact portion of the n-type MIS transistor formed on the semiconductor substrate near the first active region;
a second substrate contact portion of the p-type MIS transistor formed on the semiconductor substrate near the second active region;
an n-type gate electrode formed over the first active region and containing an n-type impurity introduced thereinto;
a first p-type doped layer formed in the first substrate contact portion and containing a p-type impurity introduced thereinto;
a p-type gate electrode formed over the second active region and containing a p-type impurity introduced thereinto; and
a first n-type doped layer formed in the second substrate contact portion and containing an n-type impurity introduced thereinto,
wherein the first active region and the first substrate contact portion are separated by a second isolation region located between the first active region and the first substrate contact portion,
the second active region and the second substrate contact portion are separated by a third isolation region located between the second active region and the second substrate contact portion,
a distance between the second substrate contact portion and the second active region is greater than a distance between the first substrate contact portion and the first active region,
a width of the first active region in the gate length direction is smaller than a width of the first substrate contact portion in the gate length direction, and
a width of the second active region in the gate length direction is smaller than a width of the second substrate contact portion in the gate length direction.
12. The semiconductor device of claim 11 , wherein
the length of a protruding part of the n-type gate electrode in the gate width direction that protrudes from the first active region toward the first substrate contact portion on the second isolation region is set equal to the length of a protruding part of the p-type gate electrode in the gate width direction that protrudes from the second active region toward the second substrate contact portion on the third isolation region.
13. The semiconductor device of claim 11 , wherein
a distance between the first substrate contact portion and the n-type gate electrode is shorter than a distance between the second substrate contact portion and the p-type gate electrode.
14. The semiconductor device of claim 11 , further comprising:
a first insulating sidewall spacer formed on a sidewall of the n-type gate electrode located opposite the first substrate contact portion; and
a second insulating sidewall spacer formed on a sidewall of the p-type gate electrode located opposite the second substrate contact portion, wherein
the first insulating sidewall spacer is extended in the direction from the second isolation region to the first substrate contact portion, and
the second insulating sidewall spacer is not formed on the second substrate contact portion, and is formed only on the third isolation region.
15. A semiconductor device having a dual-gate structure, the device comprising:
a first active region of an n-type MIS transistor and a second active region of a p-type MIS transistor formed on a semiconductor substrate so as to be adjacent to each other with a first isolation region interposed therebetween;
a first substrate contact portion of the n-type MIS transistor formed on the semiconductor substrate near the first active region;
a second substrate contact portion of the p-type MIS transistor formed on the semiconductor substrate near the second active region;
an n-type gate electrode formed over the first active region and containing an n-type impurity introduced thereinto;
a p-type doped layer formed in the first substrate contact portion and containing a p-type impurity introduced thereinto;
a p-type gate electrode formed over the second active region and containing a p-type impurity introduced thereinto; and
an n-type doped layer formed in the second substrate contact portion and containing an n-type impurity introduced thereinto,
wherein the first active region and the first substrate contact portion are separated by a second isolation region located between the first active region and the first substrate contact portion,
the second active region and the second substrate contact portion are separated by a third isolation region located between the second active region and the second substrate contact portion,
the length of a protruding part of the p-type gate electrode in the gate width direction that protrudes from the second active region toward the second substrate contact portion on the third isolation region is shorter than the length of a protruding part of the n-type gate electrode in the gate width direction that protrudes from the first active region toward the first substrate contact portion on the second isolation region,
a width of the first active region in the gate length direction is smaller than a width of the first substrate contact portion in the gate length direction, and
a width of the second active region in the gate length direction is smaller than a width of the second substrate contact portion in the gate length direction.
16. The semiconductor device of claim 15 , wherein a distance between the second substrate contact portion and the second active region is set equal to a distance between the first substrate contact portion and the first active region.
17. The semiconductor device of claim 15 , wherein
a distance between the first substrate contact portion and the n-type gate electrode is shorter than a distance between the second substrate contact portion and the p-type gate electrode.
18. The semiconductor device of claim 15 , further comprising:
a first insulating sidewall spacer formed on a sidewall of the n-type gate electrode located opposite the first substrate contact portion; and
a second insulating sidewall spacer formed on a sidewall of the p-type gate electrode located opposite the second substrate contact portion, wherein
the first insulating sidewall spacer is extended in the direction from the second isolation region to the first substrate contact portion, and
the second insulating sidewall spacer is not formed on the second substrate contact portion, and is formed only on the third isolation region.