Data processing system
A data processing system includes: a processor; a first memory for storing data which is accessed by the processor; a second memory having an area in which transferred data is stored; and a data control section for making a data transfer section transfer data from the first memory to the area in the second memory in accordance with an access request made by the processor, and storing area information indicating the data stored in the area. If data accessed by the processor is the data indicated by the area information, the data control section makes the processor access the second memory.
1 . A data processing system, comprising:
a processor;
a first memory for storing data which is accessed by the processor;
a second memory having an area in which transferred data is stored;
a first access controller for controlling access to the first memory;
a second access controller for controlling access to the second memory;
a data transfer section for transferring data from the first memory to the second memory through the first and second access controllers; and
a data control section for making the data transfer section transfer data from the first memory, to the area in the second memory in accordance with an access request made by the processor, and storing area information indicating the data stored in the area,
wherein if data accessed by the processor is the data indicated by the area information, the data control section makes the processor access the second memory.
2 . The data processing system of claim 1 , wherein the first access controller controls access to the first memory so that the processor can access data of the first memory irrespective of whether the first memory is a memory that cannot be accessed without a certain routine or the first memory is a memory that is accessible by an address received from an address bus.
3 . The data processing system of claim 2 , wherein the first access controller allows the processor to access data of the first memory by using the same address space irrespective of whether the first memory is a memory that cannot be accessed without a certain routine or the first memory is a memory that is accessible by an address received from an address bus.
4 . The data processing system of claim 1 , wherein, at the time of start-up of the data processing system, the data transfer section automatically transfers data in a certain area in the first memory to the second memory.
5 . The data processing system of claim 1 , wherein the data control section changes the size of the area in accordance with a request from the processor.
6 . The data processing system of claim 1 , wherein the data transfer section includes a buffer memory for storing therein data that is being transferred from the first memory to the second memory; and
if the data to which access has been requested by the processor matches the data stored in the buffer memory, the data control section makes the processor read that data from the buffer memory.
7 . The data processing system of claim 1 , wherein the data control section further transfers data in an area following an area where the data which has been accessed by the processor is stored, from the first memory to the second memory.
8 . The data processing system of claim 1 , wherein the second memory includes a plurality of said areas; and
the data control section determines, in accordance with a certain criterion, one of the plurality of areas that is to be overwritten, and instructs the data transfer section to overwrite the determined area.
9 . The data processing system of claim 8 , wherein the data control section makes the determination in accordance with a priority assigned to data stored in each of the plurality of areas.