Semiconductor device and fabrication method thereof

1. A semiconductor device comprising a first MIS transistor on a first active region of a semiconductor substrate, the first MIS transistor including:

a first gate insulating film provided on the first active region;

a first gate electrode provided on the first gate insulating film;

a first stressor insulating film provided on an upper face and side faces facing in a gate length direction of the first gate electrode such that first stress acts on a channel of the first MIS transistor in the gate length direction;

a first base insulating film provided on side faces of the first gate electrode facing in a gate width direction; and

a first side wall provided between the side faces of the first gate electrode facing in the gate length direction and the first stressor insulating film,

wherein the side faces of the first gate electrode facing in the gate width direction are not covered with the first stressor insulating film,

the first active region is surrounded by an isolation region formed in the semiconductor substrate,

an edge of the first stressor insulating film in the gate width direction is located on a part of the first gate electrode existing on the isolation region, and

the first side wall does not exist between the side faces of the first gate electrode facing in the gate width direction and the first base insulating film.

2. The semiconductor device of claim 1 , wherein:

the first base insulating film is a second stressor insulating film which causes second stress on the channel of the first MIS transistor in the gate width direction;

the first stress is any one of compressive stress and tensile stress; and

the second stress is the other one of compressive stress and tensile stress.

3. The semiconductor device of claim 2 , wherein:

the first MIS transistor is a P-type MIS transistor;

the first stress is compressive stress; and

the second stress is tensile stress.

4. The semiconductor device of claim 3 , wherein:

a principal surface of the semiconductor substrate is (100) surface; and

the gate length direction of the first gate electrode is <110> direction.

5. The semiconductor device of claim 2 , wherein:

the first MIS transistor is an N-type MIS transistor;

the first stress is tensile stress; and

the second stress is compressive stress.

6. The semiconductor device of claim 5 , wherein:

a principal surface of the semiconductor substrate is (100) surface; and

the gate length direction of the first gate electrode is <100> direction.

7. The semiconductor device of claim 2 , further comprising a second MIS transistor provided on a second active region of the semiconductor substrate, the second MIS transistor including a second gate insulating film provided on the second active region, a second gate electrode provided on the second gate insulating film, and a second base insulating film provided on the second gate electrode,

wherein the second base insulating film is a third stressor insulating film which causes third stress on a channel of the second MIS transistor,

the third stressor insulating film and the second stressor insulating film are made of a same insulating film,

the second active region is surrounded by the isolation region formed in the semiconductor substrate, and

the first active region and the second active region are separated from each other by the isolation region.

8. The semiconductor device of claim 7 , wherein:

the first MIS transistor is a P-type MIS transistor;

the second MIS transistor is an N-type MIS transistor;

the first stress is compressive stress;

the second stress is tensile stress; and

the third stress is tensile stress.

9. The semiconductor device of claim 8 , wherein:

a principal surface of the semiconductor substrate is (100) surface; and

the gate length direction of the first and second gate electrodes is <110> direction.

10. The semiconductor device of claim 7 , wherein:

the first MIS transistor is an N-type MIS transistor;

the second MIS transistor is a P-type MIS transistor;

the first stress is tensile stress;

the second stress is compressive stress; and

the third stress is compressive stress.

11. The semiconductor device of claim 10 wherein:

a principal surface of the semiconductor substrate is (100) surface; and

the gate length direction of the first and second gate electrodes is <100> direction.

12. The semiconductor device of claim 7 , wherein

the second MIS transistor further includes a second side wall provided on side faces of part of the second gate electrode which exists over the second active region; and

the second side wall does not exist between side faces of part of the second gate electrode which exists over the isolation region and the third stressor insulating film.

13. The semiconductor device of claim 1 , wherein:

the first side wall is provided on side faces of part of the first gate electrode which exists over the first active region; and

the first side wall does not exist between side faces facing in the gate length direction of part of the first gate electrode which exists over the isolation region and the first stressor insulating film or between side faces facing in the gate width direction of the part of the first gate electrode which exists over the isolation region and the first base insulating film.

14. The semiconductor device of claim 1 , further comprising a second MIS transistor provided on a second active region of the semiconductor substrate, the second MIS transistor including:

a second gate insulating film provided on the second active region;

a second gate electrode provided on the second gate insulating film; and

a second base insulating film provided on the second gate electrode,

wherein the second active region is surrounded by the isolation region formed in the semiconductor substrate, and

the first active region and the second active region are separated from each other by the isolation region.

15. The semiconductor device of claim 14 , wherein the second MIS transistor further includes a second side wall provided between side faces of the second gate electrode and the second base insulating film.