Semiconductor IC and testing method thereof
View Patent ↗According to the present invention, the outputs of the last scanning flip-flop circuits 12 included in scan chains 111 are compiled and compressed in an output compression circuit 112 , a sum of the outputs from the scan chains 111 and an expected value written in an expected value storage circuit 113 from the outside are compared with each other in an expected value decision circuit 114 , the sum being outputted from the output compression circuit 112 , a pass/fail decision result obtained by the comparison can be outputted from an output terminal 116 of the expected value decision circuit 114 to the outside, and the decision result can be stored regardless of the reset of a system.
1. A semiconductor IC, comprising:
combinational circuits;
a plurality of scan chains;
an output compression circuit fed with outputs of last ones of scanning flip-flop circuits included in the scan chains, and compiling outputs of the scan chains;
an expected value storage circuit capable of writing an expected value from outside; and
an expected value decision circuit fed with an output compressed by the output compression circuit and the expected value of the expected value storage circuit;
wherein the expected value storage circuit writes the expected value from the outside through an output terminal of the expected value decision circuit; and
the expected value decision circuit has a function of comparing the compressed output of the output compression circuit and the expected value of the expected value storage circuit and outputting a decision result from the output terminal to the outside.