Array substrate for liquid crystal display device and method of fabricating the same

1. An array substrate for a liquid crystal display device, comprising:

a data line on a substrate;

a source electrode contacting and overlapping the data line, a drain electrode spaced apart from the source electrode and a pixel electrode connected to the drain electrode, wherein the source electrode, the drain electrode and the pixel electrode each include transparent conductive material;

a data pad at one end of the data line, wherein the data pad is disposed in a same layer as the data line;

a data pad terminal on the data pad, wherein the data pad terminal includes a same material as the source and drain electrodes and the data pad terminal is disposed in a same layer as the source and drain electrodes;

an organic semiconductor layer contacting the source and drain electrodes;

a gate insulating layer on the organic semiconductor layer;

a gate electrode on the gate insulating layer;

a first passivation layer on the gate electrode, the first passivation layer having a gate contact hole exposing the gate electrode; and

a gate line on the first passivation layer, the gate line connected to the gate electrode through the gate contact hole.

2. The array substrate according to claim 1 , wherein the transparent conductive material includes indium-tin-oxide (ITO).

3. The array substrate according to claim 1 , wherein the source and drain electrodes each include a material having a higher work function than a material of the data line.

4. The array substrate according to claim 1 , wherein the pixel electrode extends from the drain electrode.

5. The array substrate according to claim 1 , wherein the gate insulating layer and the gate electrode have substantially a same shape as the organic semiconductor layer.

6. The array substrate according to claim 1 , further comprising a gate pad at one end of the gate line.

7. The array substrate according to claim 6 , wherein the first passivation layer further has a data pad contact hole exposing the data pad terminal and an open portion exposing the pixel electrode.

8. The array substrate according to claim 1 , wherein the gate line and the pixel electrode overlap each other to form a storage capacitor.

9. The array substrate according to claim 1 , further comprising a second passivation layer on the gate line.

10. Original) The array substrate according to claim 1 , further comprising a buffer layer between the substrate and the organic semiconductor layer, wherein the buffer layer has a hydrophilic property.

11. A method of fabricating an array substrate for a liquid crystal display device, comprising:

forming a data line on a substrate;

forming a source electrode contacting and overlapping the data line, a drain electrode spaced apart from the source electrode and a pixel electrode extending from the drain electrode, wherein the source electrode, the drain electrode and the pixel electrode each include a transparent conductive material;

forming a data pad at one end of the data line;

forming a data pad terminal on the data pad, wherein the data pad terminal is formed simultaneously with the source and drain electrodes;

forming an organic semiconductor layer contacting the source and drain electrodes, a gate insulating layer on the organic semiconductor layer and a gate electrode on the gate insulating layer;

forming a first passivation layer on the gate electrode, the first passivation layer having a gate contact hole exposing the gate electrode; and

forming a gate line on the first passivation layer, the gate line connected to the gate electrode through the gate contact hole.

12. The method according to claim 11 , wherein the transparent conductive material includes indium-tin-oxide (ITO).

13. The method according to claim 11 , further comprising treating the source and drain electrodes with oxygen (O2) plasma.

14. A method of fabricating an array substrate for a liquid crystal display device, comprising:

forming a data line on a substrate;

forming a source electrode contacting and overlapping the data line, a drain electrode spaced apart from the source electrode and a pixel electrode extending from the drain electrode, wherein the source electrode, the drain electrode and the pixel electrode each include a transparent conductive material;

forming an organic semiconductor layer contacting the source and drain electrodes, a gate insulating layer on the organic semiconductor layer and a gate electrode on the gate insulating layer;

forming a first passivation layer on the gate electrode, the first passivation layer having a gate contact hole exposing the gate electrode; and

forming a gate line on the first passivation layer, the gate line connected to the gate electrode through the gate contact hole,

wherein forming the organic semiconductor layer, the gate insulating layer and the gate electrode includes:

forming an organic semiconductor material layer on the source electrode, the drain electrode and the pixel electrode;

forming an organic insulating material layer on the organic semiconductor material layer;

forming a metallic material layer on the organic insulating material layer;

forming a photoresist pattern on the metallic material layer;

patterning the metallic material layer using the photoresist pattern as an etch mask through a first etching process;

removing the photoresist pattern; and

patterning the organic insulating material layer and the organic semiconductor material layer using the gate electrode as an etch mask through a second etching process.

15. The method according to claim 14 , wherein the organic semiconductor material layer is formed using one of an inkjet coating method, a nozzle coating method, a bar coating method, a slit coating method, a spin coating method and a printing method.

16. The method according to claim 11 , further comprising forming a gate pad at one end of the gate line.

17. The method according to claim 16 , wherein the first passivation layer further has a data pad contact hole exposing the data pad terminal and an open portion exposing the pixel electrode.

18. The method according to claim 11 , wherein the gate line and the pixel electrode overlap each other to form a storage capacitor.

19. The method according to claim 11 , further comprising forming a second passivation layer on the gate line.

20. The method according to claim 11 , further comprising forming a buffer layer between the substrate and the organic semiconductor layer, wherein the buffer layer has a hydrophilic property.