Method and apparatus for detecting lock status of a GPS signal

1. A method for detecting lock status of a spread spectrum signal digitized at a predetermined frequency, comprising:

producing a first data stream by multiplying the spread spectrum signal with an in-phase signal;

producing a second data stream by multiplying the spread spectrum signal with a quadrature signal;

calculating a first integration result in an integration unit based on the first data stream and a predetermined pseudorandom noise code (PRN code), the PRN code having a same phase shift as the first data stream;

calculating a second integration result in the integration unit based on the second data stream and the predetermined PRN code, the PRN code having a same phase shift as the second data stream;

determining a first and second evaluation values in a lock status detector based on the first and second integration results;

determining a ratio by dividing the first evaluation value by the second evaluation value;

determining a lock status result in the lock status detector by comparing the ratio with a predetermined value, the lock status result indicating whether the spread spectrum signal is locked or lost;

producing multiple lock status results over a time period;

determining that the spread spectrum signal is locked when a first predetermined number of lock status results indicating the spread spectrum signal is locked have been produced consecutively; and

determining that the spread spectrum signal is lost when a second predetermined number of lock status results indicating the spread spectrum signal is lost have been produced consecutively.

2. The method of claim 1 , wherein determining the first evaluation value comprising:

accumulating the first and second integration results to produce a first and second accumulated results, respectively, over a time period; and

calculating a sum of squares of the first and second accumulated results.

3. The method of claim 2 , wherein determining the second evaluation value comprising:

calculating a sum of squares of the first and second integration results; and

accumulating the sum of squares over the time period.

4. The method of claim 1 , wherein determining the first evaluation value comprising:

accumulating the first and second integration results to produce a first and second accumulated results, respectively, over a time period;

calculating a sum of squares of the first and second accumulated results; and

calculating a square root of the sum of squares.

5. The method of claim 4 , wherein determining the second evaluation value comprising:

calculating a sum of squares of the first and second integration results;

calculating a square root of the sum of squares; and

accumulating the square root over the time period.

6. The method of claim 1 , wherein determining the first evaluation value comprising:

accumulating the first and second integration results to produce a first and second accumulated results, respectively, over a time period; and

calculating a sum of absolute values of the first and second accumulated results.

7. The method of claim 6 , wherein determining the second evaluation value comprising:

calculating a sum of absolute values of the first and second integration results; and

accumulating the sum of absolute values over the time period.

8. The method of claim 1 , further comprising:

filtering the first and second evaluation values in a filtering unit before determining the ratio.

9. The method of claim 1 , further comprising:

detecting boundaries of navigation data bits; and

accumulating the first and second integration results within the period of a navigation data bit.

10. An apparatus for detecting lock status of a spread spectrum signal digitized at a predetermined frequency, comprising:

a first accumulator for accumulating an in-phase integration result and a quadrature integration result separately, over a time period;

a first calculation unit coupled to the first accumulator for determining a first evaluation value based on the accumulated in-phase integration result and the accumulated quadrature integration result;

a second calculation unit for processing the in-phase integration result and the quadrature integration result;

a second accumulator coupled to the second calculation unit for accumulating an output of the second calculation unit over the time period;

a multiplier for determining a second evaluation value by multiplying the accumulated result from the second accumulator with a predetermined value; and

a comparator coupled to the first calculation unit and the multiplier for comparing the first and second evaluation results and generating a comparison result, the comparison result being an indicator of the lock status.

11. The apparatus of claim 10 , further comprising:

a state machine coupled to the comparator for determining the lock status.

12. The apparatus of claim 10 , wherein the first calculation unit calculates a sum of squares of the accumulated in-phase integration result and the accumulated quadrature integration result.

13. The apparatus of claim 12 , wherein the second calculation unit calculates a sum of squares of the in-phase integration result and the quadrature integration result.

14. The apparatus of claim 10 , wherein the first calculation unit first calculates a sum of squares of the accumulated in-phase integration result and the accumulated quadrature integration result, and then calculates a square root of the sum of squares.

15. The apparatus of claim 14 , wherein the second calculation unit first calculates a sum of squares of the in-phase integration result and the quadrature integration result, and then calculates a square root of the sum of squares.

16. The apparatus of claim 10 , wherein the first calculation unit calculates a sum of absolute values of the accumulated in-phase integration result and the accumulated quadrature integration result.

17. The apparatus of claim 16 , wherein the second calculation unit calculates a sum of absolute values of the in-phase integration result and the quadrature integration result.

18. The apparatus of claim 10 , further comprising:

a first filter coupled between the first calculation unit and the comparator; and

a second filter coupled between the multiplier and the comparator.

19. The apparatus of claim 10 , wherein the time period is the period of a navigation data bit.

20. A system for processing a spread spectrum signal digitized at a predetermined sampling frequency, comprising:

an acquisition module; and

a tracking module coupled to the acquisition module, comprising:

a first integration unit being capable of producing an in-phase integration result;

a second integration unit being capable of producing a quadrature integration result;

a bit synchronization module for detecting bit boundaries of navigation data bits;

a lock status detector coupled to the first and second integration unit, for detecting lock status of the spread spectrum signal, wherein the lock status detector comprising:

a first accumulator for accumulating an in-phase integration result and a quadrature integration result separately, over a time period;

a first calculation unit coupled to the first accumulator for determining a first evaluation value based on the accumulated in-phase integration result and the accumulated quadrature integration result;

a second calculation unit for processing the in-phase integration result and the quadrature integration result;

a second accumulator coupled to the second calculation unit for accumulating an output of the second calculation unit over the time period;

a multiplier for determining a second evaluation value by multiplying the accumulated result from the second accumulator with a predetermined value; and

a comparator coupled to the first calculation unit and the multiplier for generating a comparison result from comparing the first and second evaluation results, the comparison result being an indicator of the lock status.

21. The system of claim 20 , wherein the lock status detector further comprising:

a state machine coupled to the comparator for determining the lock status.

22. The system of claim 20 , wherein the first calculation unit calculates a sum of squares of the accumulated in-phase integration result and the accumulated quadrature integration result.

23. The system of claim 22 , wherein the second calculation unit calculates a sum of squares of the in-phase integration result and the quadrature integration result.

24. The system of claim 20 , wherein the first calculation unit first calculates a sum of squares of the accumulated in-phase integration result and the accumulated quadrature integration result, and then calculates a square root of the sum of squares.

25. The system of claim 24 , wherein the second calculation unit first calculates a sum of squares of the in-phase integration result and the quadrature integration result, and then calculates a square root of the sum of squares.

26. The system of claim 20 , wherein the first calculation unit calculates a sum of absolute values of the accumulated in-phase integration result and the accumulated quadrature integration result.

27. The system of claim 26 , wherein the second calculation unit calculates a sum of absolute values of the in-phase integration result and the quadrature integration result.

28. The system of claim 20 , wherein the lock status detector further comprising:

a first filter coupled between the first calculation unit and the comparator; and

a second filter coupled between the multiplier and the comparator.

29. The system of claim 20 , wherein the time period is the period of a navigation data bit.