IP Library Granted Patent US 8,046,660
Granted Patent B2
US 8,046,660 · App. 11/820,934 · Granted Oct 25, 2011

System and method for correcting errors in non-volatile memory using product codes

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Quick Facts
Patent No.
US 8,046,660
App. No.
11/820,934
Granted
Oct 25, 2011
Kind
B2
Abstract

A product code encoder for non-volatile (NV) memory includes a first encoder that encodes data in codewords in a first dimension that is stored in the NV memory. The product code encoder also includes a second encoder that encodes data in codewords in a second dimension that is stored in the NV memory. A product code codeword is based on the codewords in the first dimension and the codewords in the second dimension.

Claims (33)

1. A non-volatile memory system, comprising:

a product code encoder including

a first encoder configured to encode data in codewords in a first dimension that is stored in a non-volatile memory; and

a second encoder configured to encode data in codewords in a second dimension that is stored in the non-volatile memory;

a product code decoder configured to perform iterative decoding on the codewords in the first dimension and the codewords in the second dimension from the non-volatile memory; and

a burst code decoder arranged parallel to the product code decoder, wherein the burst code decoder is configured to perform burst error decoding on the codewords in the first dimension and the codewords in the second dimension while the product code decoder performs the iterative decoding.

2. The non-volatile memory system of claim 1 , wherein at least one of the codewords in the first dimension and the codewords in the second dimension is based on a code selected from a group consisting of a Hamming code, a Reed-Solomon (RS) code, a Bose-Chaudhuri-Hochquenghem (BCH) binary code, a cyclic redundancy code, a Golay code, a Reed-Muller code, a Goppa code, low-density parity-check (LDPC) codes, turbo codes, convolutional codes, trellis coded modulation (TCM), block coded modulation (BCM).

3. The non-volatile memory system of claim 1 , wherein at least one of the first and second encoders comprises a product code encoder.

4. The non-volatile memory system of claim 1 , wherein a product code codeword is based on a product of the codewords in the first dimension and the codewords in the second dimension.

5. The non-volatile memory system of claim 1 , wherein the first dimension comprises a row and the second dimension comprises a column.

6. The non-volatile memory system of claim 1 , further comprising:

the non-volatile memory, wherein the non-volatile memory comprises at least one of flash memory, static random access memory (SRAM), nitride read only memory (NROM), magnetic RAM, and phase-change memory (PRAM).

7. The non-volatile memory system of claim 1 , further comprising:

a modulator configured to modulate signals from the product code encoder during a write operation; and

a demodulator configured to demodulate data stored in the non-volatile memory during a read operation.

8. The non-volatile memory system of claim 1 , wherein the product code decoder comprises a row decoder configured to decode the codewords in the first dimension, and

a column decoder configured to decode the codewords in the second dimension.

9. The non-volatile memory system of claim 8 , wherein when the row decoder is configured to detect an error in one of the codewords in the first dimension, the one of the codewords in the first dimension is marked as an erasure.

10. The non-volatile memory system of claim 9 , wherein the column decoder is configured to detect another error in one of the codewords in the second dimension based on the erasure.

11. The non-volatile memory system of claim 10 , wherein the product code decoder is configured to iterate between the row and column decoders to determine other errors in the codewords in the first dimension and the codewords in the second dimension.

12. The non-volatile memory system of claim 8 , wherein the row decoder determines that one of the codewords in the first dimension is miscorrected based on a number of errors in the codeword in the first dimension and erases the codeword in the first dimension.

13. The non-volatile memory system of claim 8 , wherein when the product code decoder fails to decode one of the codewords in the second dimension, the product code decoder erases a number of least reliable codewords in the first dimension and repeats decoding for the one of the codewords in the second dimension.

14. The non-volatile memory system of claim 8 , wherein when the product code decoder decodes one of the codewords in the second dimension but alters a symbol in one of the codewords in the first dimension, the product code decoder erases a number of least reliable codewords in the first dimension and repeats decoding for the one of the codewords in the second dimension.

15. The non-volatile memory system of claim 1 , further comprising N encoders that encode data in codewords in N dimensions that is stored in the non-volatile memory, wherein a product code codeword is based on a product of said codewords in the N dimensions, where N is an integer greater than or equal to three.

16. A method for encoding a product code, the method comprising:

encoding data in codewords in a first dimension that is stored in a non-volatile memory;

encoding data in codewords in a second dimension that is stored in the non-volatile memory;

performing iterative decoding on the codewords in the first dimension and the codewords in the second dimension from the non-volatile memory; and

performing burst error code decoding on the codewords in the first dimension and the codewords in the second dimension while performing the iterative decoding.

17. The method of claim 16 , wherein at least one of the codewords in the first dimension and the codewords in the second dimension is based on a code selected from a group consisting of a Hamming code, a Reed-Solomon (RS) code, a Bose-Chaudhuri-Hochquenghem (BCH) binary code, a cyclic redundancy code, a Golay code, a Reed-Muller code, a Goppa code, low-density parity-check (LDPC) codes, turbo codes, convolutional codes, trellis coded modulation (TCM), block coded modulation (BCM).

18. The method of claim 16 , wherein a product code codeword is based on a product of the codewords in the first dimension and the codewords in the second dimension.

19. The method of claim 16 , wherein the first dimension comprises a row and the second dimension comprises a column.

20. The method of claim 16 , further comprising encoding data in codewords in N dimensions that is stored in the non-volatile memory, wherein a product code codeword is based on a product of the codewords in the N dimensions, where N is an integer greater than or equal to three.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2020
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 051778/0537 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 6, 2007
From: MARVELL INTERNATIONAL LTD.
To: MARVELL WORLD TRADE LTD.
Reel/Frame 019652/0463 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2007
From: WU, ZINING; SUTARDJA, PANTAS
To: MARVELL SEMICONDUCTOR, INC.
Reel/Frame 019506/0920 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2007
From: MARVELL SEMICONDUCTOR, INC.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 019509/0404 →