Integrated circuit including power diode
View Patent ↗A method of fabricating a semiconductor integrated circuit including a power diode includes providing a semiconductor substrate of first conductivity type, fabricating a integrated circuit such as a CMOS transistor circuit in a first region of the substrate, and fabricating a power diode in a second region in the semiconductor substrate. Dielectric material is formed between the first region and the second regions thereby providing electrical isolation between the integrated circuit in the first region and the power diode in the second region. The power diode can comprise a plurality of MOS source/drain elements and associated gate elements all connected together by one electrode of the diode, and a semiconductor layer in the second region can function as another source/drain of the power diode.
1. A semiconductor integrated circuit comprising:
a) semiconductor substrate having material of a first conductivity type,
b) a first region in said substrate in which an integrated circuit is fabricated,
c) a second region in said substrate having material of a second conductivity type in which a power diode is fabricated, wherein the second regions comprises a first subregion having a first concentration of material of the second conductivity type, and a second subregion having a second concentration of material of the second conductivity type, wherein the power diode includes a conductive layer on a surface of the substrate functioning as a first electrode, and a conductive via extending from the surface into the substrate and contacting semiconductor material of the second conductivity type which functions as a second electrode, and
d) dielectric material between the first region and the second region providing electrical isolation between the first region and the second region, wherein the power diode comprises a plurality of MOS source/drain elements and associated gate elements all connected together by the first electrode, a semiconductor layer of a second conductivity type in the second region and in which the plurality of MOS source/drain elements are fabricated, the semiconductor layer being contacted by the second electrode.
2. The integrated circuit of claim 1 where the dielectric material comprises silicon oxide formed in a surface of the semiconductor substrate, and the second region includes implanted dopant of a second conductivity type.
3. The integrated circuit of claim 1 wherein the dielectric material comprises silicon oxide.
4. The integrated circuit as defined by claim 1 wherein the second region includes epitaxial semiconductor material grown in a trench in one surface of the substrate, and the dielectric material comprises spacers formed on sidewalls of the trench.
5. The integrated circuit as defined by claim 1 wherein each MOS source/drain element is electrically connectable to the semiconductor layer through a channel controlled by a gate element.
6. The integrated circuit as defined by claim 5 wherein each channel is laterally graded under a gate element with a sloped P-N junction separating the channel region from the semiconductor layer.
7. The integrated circuit as defined by claim 6 wherein the P-N junction underlies all of the gate element to provide reduced reverse bias leakage current.
8. The integrated circuit as defined by claim 7 wherein the dielectric material comprises silicon oxide formed in a surface of the semiconductor substrate, and the second region includes implanted dopant of a second conductivity type.
9. The integrated circuit as defined by claim 1 wherein the dielectric material comprises silicon oxide.
10. The integrated circuit as defined by claim 1 wherein the second region includes epitaxial semiconductor material grown in a trench in surface of the substrate, and the dielectric material comprises spacers formed on side walls of the trench.