Method of manufacturing a semiconductor integrated circuit and semiconductor integrated circuit
View Patent ↗A semiconductor integrated circuit is provided in which a CMOS transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film. Second conductivity type source and drain regions are formed in the semiconductor film. The source region has an ultra-shallow high-density second conductivity type source extension region at a boundary with a channel region, a low-density second conductivity type source extension region under the ultra-shallow high-density second conductivity type source extension region, and a high-density second conductivity type source extension region under the low-density second conductivity type source extension region. The drain region has an ultra-shallow high-density second conductivity type drain extension region at a boundary with the channel region, a low-density second conductivity type drain extension region under the ultra-shallow high-density second conductivity type drain extension region, and a high-density second conductivity type drain extension region under the low-density second conductivity type drain extension region. A gate insulating film is formed on an upper surface of the semiconductor film. A gate electrode is formed on an upper surface of the gate insulating film.
1. A semiconductor integrated circuit in which a CMOS transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film, the semiconductor integrated circuit comprising:
a second conductivity type source region formed in the semiconductor film, the source region having an ultra-shallow high-density second conductivity type source extension region at a boundary with a channel region, a low-density second conductivity type source extension region under the ultra-shallow high-density second conductivity type source extension region, and a high-density second conductivity type source extension region under the low-density second conductivity type source extension region;
a second conductivity type drain region formed in the semiconductor film, the drain region having an ultra-shallow high-density second conductivity type drain extension region at a boundary with the channel region, a low-density second conductivity type drain extension region under the ultra-shallow high-density second conductivity type drain extension region, and a high-density second conductivity type drain extension region under the low-density second conductivity type drain extension region;
a gate insulating film formed on an upper surface of the semiconductor film; and
a gate electrode formed on an upper surface of the gate insulating film.
2. A semiconductor integrated circuit according to claim 1 ; further comprising a first sidewall disposed around the gate electrode and a second sidewall disposed on the first sidewall.
3. A semiconductor integrated circuit according to claim 1 ; wherein the ultra-shallow high-density second conductivity type source extension region, the low-density second conductivity type source extension region, and the high-density second conductivity type source extension region are stacked in a thickness direction of the semiconductor film.
4. A semiconductor integrated circuit according to claim 3 ; wherein the ultra-shallow high-density second conductivity type drain extension region, the low-density second conductivity type drain extension region, and the high-density second conductivity type drain extension region are stacked in a thickness direction of the semiconductor film.
5. A semiconductor integrated circuit according to claim 1 ; wherein the ultra-shallow high-density second conductivity type drain extension region, the low-density second conductivity type drain extension region, and the high-density second conductivity type drain extension region are stacked in a thickness direction of the semiconductor film.
6. A semiconductor integrated circuit according to claim 1 ; wherein each of the source region and the drain region has a second conductivity type high-density source region and a second conductivity type high-density drain region, respectively, disposed on respective opposite sides of the gate electrode.
7. A semiconductor integrated circuit according to claim 6 ; wherein the second conductivity type high-density source region and the second conductivity type high-density drain region are adjacent the extension regions of the source region and the extension regions of the drain region, respectively.
8. A semiconductor integrated circuit according to claim 7 ; wherein the extension regions of the source region are stacked vertically along an edge of the source region; and wherein the extension regions of the drain region are stacked vertically along an edge of the drain region.
9. A semiconductor integrated circuit according to claim 6 ; wherein the extension regions of the source region are stacked vertically along an edge of the source region; and wherein the extension regions of the drain region are stacked vertically along an edge of the drain region.
10. A semiconductor integrated circuit according to claim 1 ; wherein the extension regions of the source region are stacked vertically along an edge of the source region; and wherein the extension regions of the drain region are stacked vertically along an edge of the drain region.