Digital-to-analog converter with dynamic element matching to minimize mismatch error
View Patent ↗In a dynamic element matching stage of a digital-to-analogue converter, in which a pair of quantizer outputs are generated, and are constrained such that their sum is equal to the parity of a received bit value, steps are taken to improve baseband noise performance. Each of the quantizers has a feedback loop associated with it, and the performance is improved by determining the quantizer outputs based on these loop values, in order to reduce the overall quantization noise. However, during time periods when these loop values are equal, there are two possible pairs of quantizer outputs that could be chosen, without adversely impacting on the overall quantization noise. the quantizer outputs are monitored during such time periods, and steps are taken to control the quantizer outputs during such time periods, in order to ensure that the two possible pairs of quantizer outputs are chosen with equal probability.
1. A digital-to-analogue converter, comprising:
a plurality of pairs of digital-to-analogue converter elements; and
an adder, connected to form an analogue output signal as the sum of the outputs of the pairs of digital-to-analogue converter elements; and further comprising:
an element matching circuit, connected to receive a digital input signal, and apply respective inputs to the pairs of digital-to-analogue converter elements, wherein the element matching circuit comprises a dynamic element matching stage associated with each of the pairs of digital-to-analogue converter elements, and wherein each dynamic element matching stage comprises:
an input for a respective stage remainder value, the remainder value having a parity determined by a value of a least significant bit thereof;
first and second quantizers, for forming a pair of quantizer outputs, a sum of said quantizer outputs being constrained to be equal to the parity of the remainder value;
first and second feedback loops, associated with the first and second quantizers respectively, for forming respective first and second loop values and applying said loop values as inputs to the first and second quantizers respectively, and
at least one integrator, for producing an output signal based on at least one of the quantizer outputs during time periods when said first and second loop values are substantially equal, wherein, during subsequent time periods when said first and second loop values are substantially equal, said quantizer outputs are controlled based on the output signal of the at least one integrator.
2. A digital-to-analogue converter as claimed in claim 1 , wherein the at least one integrator produces an output signal based on the numbers of positive and negative quantizer output values during time periods when said first and second loop values are substantially equal, and wherein the quantizers are controlled to produce quantizer outputs having substantially equal numbers of positive and negative values.
3. A digital-to-analogue converter as claimed in claim 2 , comprising:
a first integrator, for counting a difference between a number of outputs of the first quantizer produced with positive values and a number of outputs of the first quantizer produced with negative values, during time periods when said first and second loop values are substantially equal; and
a second integrator, for counting a difference between a number of outputs of the second quantizer produced with positive values and a number of outputs of the second quantizer produced with negative values, during time periods when said first and second loop values are substantially equal.
4. A digital-to-analogue converter as claimed in claim 1 , wherein the at least one integrator produces an output signal based on quantizer error values during time periods when said first and second loop values are substantially equal, and wherein, when said first and second loop values are substantially equal, a quantization error is measured, and the quantizers are controlled to minimize said quantization error.
5. A digital-to-analogue converter as claimed in claim 4 , wherein said at least one integrator forms an integrated value of a difference between a quantizer output and a quantizer input for one of said quantizers.
6. An audio device, comprising a digital-to-analogue converter as claimed in claim 1 .
7. An electronic device, including an audio device, and comprising a digital-to-analogue converter as claimed in claim 1 .
8. A computer-readable medium, comprising software code for implementing a digital-to-analogue converter as claimed in claim 1 .
9. A method of operation of a digital-to-analogue converter, wherein the digital-to-analogue converter comprises:
a plurality of pairs of digital-to-analogue converter elements; and
an adder, connected to form an analogue output signal as the sum of the outputs of the pairs of digital-to-analogue converter elements;
an element matching circuit, connected to receive a digital input signal, and apply respective inputs to the pairs of digital-to-analogue converter elements, wherein the element matching circuit comprises a dynamic element matching stage associated with each of the pairs of digital-to-analogue converter elements, and wherein each dynamic element matching stage comprises:
an input for a respective stage remainder value, the remainder value having a parity determined by a value of a least significant bit thereof;
first and second quantizers, for forming a pair of quantizer outputs;
first and second feedback loops, associated with the first and second quantizers respectively, for forming respective first and second loop values and applying said loop values as inputs to the first and second quantizers respectively,
the method comprising, in at least one dynamic element matching stage:
producing an output signal based on at least one of the quantizer outputs during time periods when said first and second loop values are substantially equal; and
during subsequent time periods when said first and second loop values are substantially equal, controlling said quantizer outputs based on said output signal, while a sum of said quantizer outputs is constrained to be equal to the parity of the respective stage remainder value.
10. A method as claimed in claim 9 , further comprising, when said first and second loop values are substantially equal, controlling the quantizers to produce quantizer outputs having substantially equal numbers of positive and negative values.
11. A method as claimed in claim 10 , further comprising:
counting a difference between a number of outputs of the first quantizer produced with positive values and a number of outputs of the first quantizer produced with negative values, during time periods when said first and second loop values are substantially equal; and
counting a difference between a number of outputs of the second quantizer produced with positive values and a number of outputs of the second quantizer produced with negative values, during time periods when said first and second loop values are substantially equal.
12. A method as claimed in claim 9 , further comprising, when said first and second loop values are substantially equal:
measuring a quantization error;
accumulating the measured quantization errors; and
controlling the quantizers to minimize said accumulated quantization error.
13. A method as claimed in claim 12 , wherein the step of measuring the quantization error comprises forming an integrated value of a difference between a quantizer output and a quantizer input for one of said quantizers.