Liquid crystal display device including step-compensating pattern and fabricating method thereof
View Patent ↗A liquid crystal display device includes first substrate having an active region and a non-active region along a peripheral portion of the active region, a second substrate facing and spaced apart from the first substrate, and having an active region and a non-active region along a peripheral portion of the active region, a seal pattern between the first and second substrates disposed along a border of the active and non-active regions, a gate line on an interior surface of the first substrate and crossing the seal pattern, a data line crossing the gate line and the seal pattern, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, a common electrode on an interior surface of the second surface, a first step-compensating pattern adjacent to the seal pattern and the gate line, a second step-compensating pattern adjacent to the seal pattern and the data line, and a liquid crystal material layer between the pixel electrode and the common electrode.
1. A liquid crystal display device, comprising:
first substrate having an active region and a non-active region along a peripheral portion of the active region;
a second substrate facing a spaced apart from the first substrate, and having an active region and a non-active region along a peripheral portion of the active region;
a seal pattern between the first and second substrates disposed along a border of the active and non-active regions;
gate lines on an interior surface of the first substrate and crossing the seal pattern;
data lines crossing the gate line and the seal pattern;
a thin film transistor connected to the gate line and the data line;
a pixel electrode connected to the thin film transistor;
a common electrode on an interior surface of the second surface;
a first step-compensating pattern overlapped by the seal pattern and positioned between two adjacent gate lines such that the first step-compensating pattern is more closely adjacent to one of the two adjacent gate lines under the seal pattern;
a second step-compensating pattern overlapped by the seal pattern and positioned between two adjacent data lines such that the second step-compensating pattern is more closely adjacent to one of the two adjacent data lines under the seal pattern; and
a liquid crystal material layer between the pixel electrode and the common electrode.
2. The device according to claim 1 , further comprising a semiconductor pattern between the first step-compensating pattern and the gate line.
3. The device according to claim 2 , wherein the semiconductor pattern has the same plan shape as the first step-compensating pattern.
4. A fabricating method of a liquid crystal display device, comprising:
forming gate lines and a first step-compensating pattern on a first substrate having an active region and a non-active region along a peripheral portion of the active region,
forming data lines crossing the gate lines and a second step-compensating pattern along the border of the active and non-active regions;
forming a first step-compensating pattern between two adjacent gate lines such that the first step-compensating pattern is more closely adjacent to one of the two adjacent gate lines;
forming a second step-compensating pattern between two adjacent data lines such that the second step-compensating pattern is more closely adjacent to one of the two adjacent data lines;
forming a thin film transistor connected to the gate line and the data line;
forming a pixel electrode connected to the thin film transistor;
forming a common electrode on an interior surface of a second surface;
forming a seal pattern along the border of the active and non-active regions, the seal pattern crossing the gate lines, the data lines, the first step-compensating pattern and the second step-compensating pattern;
attaching the first and second substrates such that the pixel electrode face the common electrode; and
forming a liquid crystal material layer between the pixel electrode and the common electrode.
5. The method according to claim 4 , further comprising forming a semiconductor pattern between the second step-compensating pattern and the gate line.