Array substrate for liquid crystal display device and method of fabricating the same
View Patent ↗An array substrate for a liquid crystal display device comprises a substrate having a pixel region, a gate line on the substrate, and a data line crossing the gate line to define the pixel region. A thin film transistor (TFT) includes a gate electrode connected to the gate line, an insulating layer on the gate electrode, an active layer on the insulating layer, an ohmic contact layer on the active layer, a source electrode connected to the data line and a drain electrode spaced apart from the source electrode. A pixel electrode connects to the drain electrode and is disposed in the pixel region. An opaque metal pattern is provided on end portions of the pixel electrode.
1. An array substrate for a liquid crystal display device, comprising:
a substrate having a pixel region;
a gate line on the substrate;
a data line crossing the gate line to define the pixel region;
a thin film transistor (TFT) including a gate electrode connected to the gate line, an insulating layer on the gate electrode, an active layer on the insulating layer, an ohmic contact layer on the active layer, a source electrode connected to the data line and a drain electrode spaced apart from the source electrode;
a pixel electrode connected to the drain electrode and disposed in the pixel region; and
an opaque metal pattern on end portions of the pixel electrode such that the pixel electrode is disposed between the substrate and the opaque metal pattern.
2. The substrate according to claim 1 , wherein the end portions of the pixel electrode are adjacent to the data line.
3. The substrate according to claim 1 , wherein the opaque metal pattern comprises molybdenum.
4. The substrate according to claim 1 , further comprising a buffer metal layer between the ohmic contact layer and the source electrode and between the ohmic contact layer and the drain electrode.
5. The substrate according to claim 1 , wherein the source electrode comprises a first source layer of a transparent conductive metallic material and a second source layer of an opaque conductive metallic material on the first source layer, and the drain electrode comprises a first drain layer of the transparent conductive metallic material and a second drain layer of the opaque conductive metallic material on the second drain layer.
6. The substrate according to claim 5 , wherein the second source layer and the second drain layer are formed of the same layer and the same material as the opaque metal pattern.
7. The substrate according to claim 5 , wherein the pixel electrode is formed of the same layer and the same material as the first drain layer.
8. The substrate according to claim 5 , wherein the data line comprises a first data layer of the transparent conductive metallic material and a second data layer of the opaque conductive metallic material.
9. The substrate according to claim 8 , wherein the transparent conductive metallic material comprises at least one of indium-tin-oxide and indium-zinc oxide.
10. The substrate according to claim 1 , wherein the active layer has a width less than a width of the gate electrode.
11. The substrate according to claim 1 , further comprising a gate pad at one end of the gate line and a gate pad terminal contacting the gate pad and including a transparent conductive metallic material.
12. The substrate according to claim 1 , further comprising a data pad at one end of the data line and including a transparent conductive metallic material.
13. The substrate according to claim 1 , wherein the pixel electrode extends and overlaps the gate line to constitute a storage capacitor having an overlapped portion of the gate line as a first storage electrode, an overlapped portion of the pixel electrode as a second storage electrode and the insulating layer as a dielectric material.