Semiconductor memory and test method for the same

1. A semiconductor memory comprising:

a plurality of main bit line pairs each composed of a main bit line and a complementary main bit line;

a plurality of sub bit line pairs each composed of a sub bit line and a complementary sub bit line and respectively corresponding to said plurality of main bit line pairs;

a plurality of word lines disposed to intersect said plurality of sub bit line pairs;

memory cells disposed on intersecting points between said sub bit line and each of said word lines and between said complementary sub bit line and each of said word lines;

a sub bit line hierarchical switch disposed correspondingly to each sub bit line between said sub bit line and a main bit line corresponding to said sub bit line;

a complementary sub bit line hierarchical switch disposed correspondingly to each complementary sub bit line between said complementary sub bit line and a complementary main bit line corresponding to said complementary sub bit line; and

a hierarchical switch control unit for turning off all of said sub bit line hierarchical switch and said complementary sub bit line hierarchical switch when a given signal is input.

2. A semiconductor memory comprising:

a plurality of main bit line pairs each composed of a main bit line and a complementary main bit line;

a plurality of sub bit line pairs each composed of a sub bit line and a complementary sub bit line and respectively corresponding to said plurality of main bit line pairs;

a plurality of word lines disposed to intersect said plurality of sub bit line pairs;

memory cells disposed on intersecting points between said sub bit line and each of said word lines and between said complementary sub bit line and each of said word lines;

a sub bit line hierarchical switch disposed correspondingly to each sub bit line between said sub bit line and a main bit line corresponding to said sub bit line;

a complementary sub bit line hierarchical switch disposed correspondingly to each complementary sub bit line between said complementary sub bit line and a complementary main bit line corresponding to said complementary sub bit line; and

a hierarchical switch control unit for turning off all of said sub bit line hierarchical switch or said complementary sub bit line hierarchical switch when a given signal is input.

3. The semiconductor memory of claim 1 , further comprising:

a sense amplifier disposed correspondingly to each of said plurality of main bit line pairs for amplifying a potential difference between a main bit line and a complementary main bit line of said main bit line pair; and

a sense amplifier control unit for deactivating said sense amplifier when a given control signal is input.

4. The semiconductor memory of claim 1 , further comprising a redundancy memory cell replaceable with each of said memory cells,

wherein a memory cell is replaced with said redundancy memory cell correspondingly to each main bit line.

5. A test method for the semiconductor memory of claim 1 , comprising:

a precharge step of precharging said plurality of main bit line pairs; and

a leakage accelerating step of supplying said given signal to said hierarchical switch control unit and increasing an absolute value of substrate potential of transistors included in said memory cells after completing the precharge step.

6. The semiconductor memory of claim 1 ,

wherein said given signal is a test mode signal.

7. The semiconductor memory of claim 1 ,

wherein said hierarchical switch control unit includes an AND circuit that receives, as inputs, said given signal and a hierarchical switch control signal and outputs a signal for controlling turn on/off of said sub bit line hierarchical switch and said complementary sub bit line hierarchical switch.

8. The semiconductor memory of claim 3 ,

wherein said sense amplifier control unit includes an AND circuit that receives, as inputs, said given signal and a sense amplifier control signal and outputs a signal for controlling activation/deactivation of said sense amplifier.

9. The semiconductor memory of claim 2 , further comprising:

a sense amplifier disposed correspondingly to each of said plurality of main bit line pairs for amplifying a potential difference between a main bit line and a complementary main bit line of said main bit line pair; and

a sense amplifier control unit for deactivating said sense amplifier when a given control signal is input.

10. The semiconductor memory of claim 2 , further comprising a redundancy memory cell replaceable with each of said memory cells,

wherein a memory cell is replaced with said redundancy memory cell correspondingly to each main bit line.

11. A test method for the semiconductor memory of claim 2 , comprising:

a precharge step of precharging said plurality of main bit line pairs; and

a leakage accelerating step of supplying said given signal to said hierarchical switch control unit and increasing an absolute value of substrate potential of transistors included in said memory cells after completing the precharge step.

12. The semiconductor memory of claim 2 ,

wherein said given signal is a test mode signal.

13. The semiconductor memory of claim 2 ,

wherein said hierarchical switch control unit includes an AND circuit that receives, as inputs, said given signal and a hierarchical switch control signal and outputs a signal for controlling turn on/off of said sub bit line hierarchical switch and said complementary sub bit line hierarchical switch.

14. The semiconductor memory of claim 9 ,

wherein said sense amplifier control unit includes an AND circuit that receives, as inputs, said given signal and a sense amplifier control signal and outputs a signal for controlling to activation/deactivation of said sense amplifier.