Semiconductor memory device

1. A semiconductor memory device comprising:

an array of memory cells arranged in a row direction and a column direction, each memory cell including a series circuit of a variable resistance element of two-port structure type and a select transistor of MOSFET type, the select transistor connected at its drain or source to one port of the variable resistance element, the select transistors in the memory cells aligned along one row connected at its gate to a common word line extending along the row direction, the memory cells aligned along one column connected at its one end to a common bit lines extending along the column direction, each of the memory cells connected at the other end to a source line extending along the row direction or the column direction; and

a voltage applying circuit for selecting one or more of the memory cells from the memory cell array and applying predetermined voltages to the word line, bit line, and source line to conduct actions of writing and reading information stored in a selected memory cell, wherein

the variable resistance element is a nonvolatile memory element capable of storing and writing information electrically by shifting an electric resistance level from a first state to a second state when a first write voltage is applied to between the two ports and shifting the electric resistance level from the second state to the first state when a second write voltage which is different in polarity and an absolute value from the first write voltage is applied to between the two ports, and

in a first writing action of shifting an electric resistance in the variable resistance element in the selected memory cell from the first state to the second state, the voltage applying circuit applies a first voltage at positive or negative polarity to between the bit line and the source line both connected to the selected memory cell with reference to the source line and a predetermined word line voltage to the word line connected to the gate of the select transistor in the selected memory cell and thus applies the first write voltage to between the two ports of the variable resistance element in the selected memory cell,

in a second writing action of shifting the electric resistance in the variable resistance element in the selected memory cell from the second state to the first state, the voltage applying circuit applies a second voltage which is opposite in the polarity to the first voltage to between the bit line and the source line both connected to the selected memory cell with reference to the source line and a predetermined word line voltage to the word line connected to the gate of the select transistor in the selected memory cell and thus applies the second write voltage to between the two ports of the variable resistance element in the selected memory cell, and

in the reading action, the voltage applying circuit applies a third voltage equal in the polarity to a reference write voltage, which is either the first write voltage for the first writing action or the second write voltage for the second writing action whichever is greater in the absolute value, to between the bit line and the source line both connected to the selected memory cell with reference to the source line and a predetermined word line voltage to the word line connected to the gate of the select transistor in the selected memory cell and thus applies a readout voltage which is lower in the absolute value than the reference write voltage to between the two ports of the variable resistance element in the selected memory cell.

2. The semiconductor memory device according to claim 1 , wherein

the memory cell includes a series circuit where the variable resistance element is connected at its one port to the source of the select transistor,

each of the select transistors in the memory cells aligned along one column is connected at its drain to the common bit line and each of the variable resistance elements in the memory cells is connected at the other port to the source line in the memory cell array,

the variable resistance element is a nonvolatile memory element for shifting the electric resistance level from a first state to a second state when receiving a first write voltage between the two ports and shifting the electric resistance level from the second state to the first state when receiving a second write voltage which is opposite in the polarity to and smaller in the absolute value than the first write voltage between the two ports, and thus can electrically store and write information, and

in the first writing action, the voltage applying circuit applies a first voltage at the positive polarity with reference to the bit line to between the bit line and the source line both connected to the selected memory cell and a predetermined word line voltage to the word line connected to the gate of the select transistor in the selected memory cell, and thus applies the first write voltage to between the two ports of the variable resistance element in the selected memory cell,

in the second writing action, the voltage applying circuit applies a second voltage at the positive polarity with reference to the source line to between the bit line and the source line both connected to the selected memory cell and a predetermined word line voltage to the word line connected to the gate of the select transistor in the selected memory cell, and thus applies the second write voltage to between the two ports of the variable resistance element in the selected memory cell, and

in the reading action, the voltage applying circuit applies a third voltage at the positive polarity with reference to the bit line to between the bit line and the source line both connected to the selected memory cell and a predetermined word line voltage to the word line connected to the gate of the select transistor in the selected memory cell, and thus applies the readout voltage which is lower in the absolute value than the first write voltage to between the two ports of the variable resistance element in the selected memory cell.

3. The semiconductor memory device according to claim 2 , wherein

the voltage applying circuit applies a grounding voltage to the bit line in the first writing action and the reading action, and the grounding voltage to the source line in the second writing action.

4. The semiconductor memory device according to claim 1 , wherein

the memory cell includes a series circuit where the variable resistance element is connected at the one port to the drain of the select transistor,

each of the select transistors in the memory cells aligned along one column is connected at its source to the common source line and each of the variable resistance elements in the memory cells is connected at the other port to the bit line in the memory cell array,

the variable resistance element is a nonvolatile memory element for shifting the electric resistance level from a first state to a second state when receiving a first write voltage between the two ports and shifting the electric resistance level from the second state to the first state when receiving a second write voltage which is opposite in the polarity to and greater in the absolute value than the first write voltage between the two ports, and thus can electrically store and write information, and

in the first writing action, the voltage applying circuit applies a first voltage at the positive polarity with reference to the bit line between the bit line and the source line both connected to the selected memory cell and a predetermined word line voltage to the word line connected to the gate of the select transistor in the selected memory cell, and thus applies the first write voltage to between the two ports of the variable resistance element in the selected memory cell,

in the second writing action, the voltage applying circuit applies a second voltage at the positive polarity with reference to the source line to between the bit line and the source line both connected to the selected memory cell and a predetermined word line voltage to the word line connected to the gate of the select transistor in the selected memory cell, and thus applies the second write voltage to between the two ports of the variable resistance element in the selected memory cell, and

in the reading action, the voltage applying circuit applies a third voltage at the positive polarity with reference to the source line to between the bit line and the source line both connected to the selected memory cell and a predetermined word line voltage to the word line connected to the gate of the select transistor in the selected memory cell, and thus applies the readout voltage which is lower in the absolute value than the second write voltage to between the two ports of the variable resistance element in the selected memory cell.

5. The semiconductor memory device according to claim 4 , wherein

the voltage applying circuit applies a grounding voltage to the bit line in the first writing action and the grounding voltage to the source line in the second writing action and the reading action.

6. The semiconductor memory device according to claim 1 , wherein

the select transistor is an n-channel MOSFET of enhancement type.

7. The semiconductor memory device according to claim 1 , wherein

a gate insulating layer of the select transistor has the same thickness as a transistor gate insulating layer of a transistor constituting peripheral circuits including the voltage applying circuit.