IP Library Granted Patent US 7,467,250
Granted Patent B2
US 7,467,250 · App. 11/827,514 · Granted Dec 16, 2008

Data transfer control device and electronic instrument generating interface signal of signal type according to interface information set in internal register

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 7,467,250
App. No.
11/827,514
Granted
Dec 16, 2008
Kind
B2
Abstract

A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus; and an internal register in which is set interface information for specifying signal types of the interface signals output from the interface circuit. The interface circuit includes first to Nth interface circuits (N is an integer greater than one), and each of the first to Nth interface circuits generates an interface signal of a signal type according to the interface information set in the internal register.

Claims (26)

1. A data transfer control method comprising:

generating a first packet that specifies interface information;

transmitting the first packet from a host-side data transfer device to a target-side data transfer device through a serial bus;

analyzing the first packet received from the host-side data transfer device by a link controller of the target-side data transfer device;

generating interface signals based on the interface information of the first packet; and

outputting the interface signals to interface bus connecting the target-side data transfer device to a plurality of target devices.

2. The data transfer control method of claim 1 ,

the first packet including a port number field for setting port number,

the target-side data transfer device outputting the interface signals to a port of the plurality of target devices connected to the interface bus, and

the port being selected from among ports of the plurality of target devices based on the port number set in the first packet.

3. The data transfer control method of claim 1 ,

the interface signals including at least one of RGB interface signals for an RGB interface, MPU interface signals for an MPU interface, and serial interface signals for a serial interface.

4. The data transfer control method of claim 1 ,

providing an internal register in the host-side data transfer device,

setting the interface information in the internal register, the interface information specifying signal types of the interface signals output from the target-side data transfer control device, and

generating the first packet based on the interface information of the internal register.

5. The data transfer control method of claim 2 ,

the internal register including register transfer start register,

generating the first packet having the interface information set in the internal register when start of transfer has instructed by using the register transfer start register, and

transmitting the first packet from the host-side data transfer device to the target-side data transfer device.

6. The data transfer control method of claim 1 ,

generating a second packet containing data in a data field and transmitting the second packet to the target-side data transfer control device after transmitting the first packet to the target-side data transfer control device.

7. The data transfer control method of claim 1 ,

the interface information including at least one of a length of a horizontal synchronization period, a length of a display period in the horizontal synchronization period, a start position of the display period in the horizontal synchronization period, a pulse width of the horizontal synchronization signal, a length of a vertical synchronization period, a length of a display period in the vertical synchronization period, a start position of the display period in the vertical synchronization period, and a pulse width of the vertical synchronization signal.

8. The data transfer control method of claim 2 ,

the interface information including at least one of a length of a horizontal synchronization period, a length of a display period in the horizontal synchronization period, a start position of the display period in the horizontal synchronization period, a pulse width of the horizontal synchronization signal, a length of a vertical synchronization period, a length of a display period in the vertical synchronization period, a start position of the display period in the vertical synchronization period, and a pulse width of the vertical synchronization signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2019
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 050197/0212 →
Priority Claims (1)
JP 2004-066029 · Mar 9, 2004 · national
Continuity (2)
Continuation 1106300700 · Feb 22, 2005
Related Publication 20070260802A1 · Nov 8, 2007