Method of forming high breakdown voltage low on-resistance lateral DMOS transistor
View Patent ↗A method of forming a metal oxide semiconductor (MOS) transistor includes the following steps. A substrate of a first conductivity is provided. A first buried layer of a second conductivity type is formed over the substrate. A second buried layer of the first conductivity type is formed in the first buried layer. An epitaxial layer of the second conductivity type is formed over the substrate. A drift region of a second conductivity type is formed in the epitaxial layer. A gate layer is formed over the drift region. A body region of the first conductivity type is formed in the drift region such that the gate overlaps a surface portion of the body region. A source region of the second conductivity is formed in the body region. A drain region of the second conductivity type is formed in the drift region. The drain region is laterally spaced from the body region. The first and second buried layers laterally extend from under the body region to under the drain region. The surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor.
1. A method of forming a metal oxide semiconductor (MOS) transistor, comprising:
providing a substrate of a first conductivity type;
forming a first buried layer of a second conductivity type in the substrate;
forming a second buried layer of the first conductivity type in the first buried layer;
forming an epitaxial layer of the second conductivity type over the substrate;
forming a drift region of a second conductivity type in the epitaxial layer;
forming a gate layer over the drift region;
forming a body region of the first conductivity type in the drift region such that the gate overlaps a surface portion of the body region;
forming a source region of the second conductivity in the body region; and
forming a drain region of the second conductivity type in the drift region, the drain region being laterally spaced from the body region;
wherein the first and second buried layers laterally extend from under the body region to under the drain region, and the surface portion of the body region extends between the source region and the drift region to form a channel region of the transistor.
2. The method of claim 1 further comprising:
forming a body-contact region of the first conductivity type in the body region; and
forming a deep region of the first conductivity type vertically extending from under the source and body-contact regions through the drift region and terminating in the second buried layer.
3. The method of claim 1 further comprising forming a field oxide between the body and drain regions, the gate extending over a portion of the field oxide.
4. The method of claim 3 wherein the field oxide is formed adjacent the drain region but is laterally spaced from the body region.
5. The method of claim 1 wherein the first buried layer forms a junction with each of the substrate, the drift region, the epitaxial layer, and the second buried layer.
6. The method of claim 1 wherein the second buried layer forms a junction with each of the first buried layer and the drift region.
7. The method of claim 1 further comprising:
forming a drain electrode contacting the drain region;
forming a source electrode contacting the source region; and
forming an interlayer dielectric layer electrically isolating the gate, the source electrode, and the drain electrode from one another.
8. The method of claim 1 wherein the first conductivity type is p-type and the second conductivity type is n-type.
9. The method of claim 1 wherein the deep region and body-contact region have a higher doping concentration than the body layer and the second buried layer.
10. The method of claim 1 wherein the drain and source regions have a higher doping concentration than the drift region and the first buried layer.