Delta-sigma modulated fractional-N PLL frequency synthesizer
View Patent ↗A delta-sigma modulated fractional-N PLL frequency synthesizer is provided. The frequency synthesizer includes a phase frequency detector for receiving a reference signal with a reference frequency (Fref) and an overflow signal to output a phase difference signal by detecting a phase and frequency difference between the reference signal and the overflow signal; a charge pump for generating an output current pulse in response to the phase difference signal; a loop filter for filtering the charge pump output current pulse and generating a corresponding control voltage; a VCO for generating a VCO output signal with a voltage controlled frequency (Fvco) in response to the control voltage; and a delta-sigma modulator, with a clock input terminal for receiving the VCO output signal, an overflow output terminal for generating the overflow signal and an integer input terminal, for determining the ratio of the VCO frequency (Fvco) and the reference frequency (Fref).
1. A fractional-N PLL frequency synthesizer, comprising:
a phase frequency detector for receiving a reference signal with a reference frequency and an overflow signal to output a phase difference signal by detecting a phase and frequency difference between the reference signal and the overflow signal;
a charge pump for generating a charge pump output current pulse in response to the phase difference signal;
a loop filter for filtering the charge pump output current pulse to correspondingly generate a control voltage;
a VCO (voltage controlled oscillator) for generating a VCO output signal with a voltage controlled frequency in response to the control voltage; and
a delta-sigma modulator, with a clock input terminal for receiving the VCO output signal, an overflow output terminal for generating the overflow signal and an input terminal for receiving an integer, for determining a ratio between the voltage controlled frequency and the reference frequency.
2. The fractional-N PLL frequency synthesizer according to claim 1 wherein the delta-sigma modulator has an accumulator size of d bits, an input integer n, and the fractional division ratio is 2 d /n.
3. The fractional-N PLL frequency synthesizer according to claim 1 wherein the delta-sigma modulator is a first-order delta-sigma modulator.
4. The fractional-N PLL frequency synthesizer according to claim 3 wherein the first-order delta-sigma modulator is implemented by an accumulator.
5. The fractional-N PLL frequency synthesizer according to claim 1 wherein the delta-sigma modulator is a second-order delta-sigma modulator.
6. The fractional-N PLL frequency synthesizer according to claim 5 wherein a duty cycle of the overflow signal of the second-order delta-sigma modulator is adjustable.
7. The fractional-N PLL frequency synthesizer according to claim 5 wherein the second-order delta-sigma modulator comprises a plurality of gain coefficients for adjusting the shaping of quantization noise.
8. The fractional-N PLL frequency synthesizer according to claim 7 wherein the values of the gain coefficients are 2 n and n is an integer.
9. The fractional-N PLL frequency synthesizer according to claim 1 wherein the width of the charge pump current pulse is proportional to a duty cycle of the phase difference signal.
10. A fractional-N PLL frequency synthesizer, comprising:
a phase frequency detector for receiving a reference signal with a reference frequency and an overflow signal to output a phase difference signal by detecting a phase and frequency difference between the reference signal and the overflow signal;
a charge pump for generating an output current pulse in response to the phase difference signal;
a loop filter for filtering the output current pulse to correspondingly generate a control voltage;
a VCO for generating a VCO output signal with a voltage controlled frequency in response to the control voltage;
a pre-scaler for receiving the VCO output signal to output a frequency divided signal by dividing the voltage controlled frequency with a first integer; and
a delta-sigma modulator, with a clock input terminal for receiving the frequency divided signal, an overflow output terminal for generating the overflow signal and a second integer input terminal for receiving a second integer,
wherein the fractional-N PLL frequency synthesizer determines a ratio between the voltage controlled frequency and the reference frequency according to the first integer and the second integer.
11. The fractional-N PLL frequency synthesizer according to claim 10 wherein the delta-sigma modulator has an accumulator size of d bits, the first integer is m, the second integer is n, and the ratio is m*2 d /n.
12. The fractional-N PLL frequency synthesizer according to claim 10 wherein the delta-sigma modulator is a first-order delta-sigma modulator.
13. The fractional-N PLL frequency synthesizer according to claim 12 wherein the first-order delta-sigma modulator is implemented by an accumulator.
14. The fractional-N PLL frequency synthesizer according to claim 10 wherein the delta-sigma modulator is a second-order delta-sigma modulator.
15. The fractional-N PLL frequency synthesizer according to claim 14 wherein a duty cycle of the overflow signal of the second-order delta-sigma modulator is adjustable.
16. The fractional-N PLL frequency synthesizer according to claim 14 wherein the second-order delta-sigma modulator is a single-loop second-order delta-sigma modulator.
17. The fractional-N PLL frequency synthesizer according to claim 14 wherein the second-order delta-sigma modulator comprises a plurality of gain coefficients for adjusting a shaping of quantization noise.
18. The fractional-N PLL frequency synthesizer according to claim 17 wherein the values of the gain coefficients are 2 n and n is an integer.
19. The fractional-N PLL frequency synthesizer according to claim 10 wherein the width of the charge pump current pulse is proportional to a duty cycle of the phase difference signal.