Tunneling effect transistor with self-aligned gate
View Patent ↗In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.
1. A method of manufacturing a semiconductor structure comprising:
forming a mandrel on a semiconductor region in a semiconductor substrate;
forming an outer dummy spacer on sidewalls of said mandrel, wherein a portion of said semiconductor region is located outside said mandrel and said outer dummy spacer;
forming a first conductivity type region in said portion of said semiconductor region;
removing said mandrel to form a recessed region and forming a second conductivity type region underneath said recessed region; and
removing said outer dummy spacer and forming a gate electrode comprising a gate dielectric and a gate conductor directly on said first conductivity type region and said second conductivity type region.
2. The method of claim 1 , further comprising performing an anneal so that said first conductivity type region and said second conductivity type region abut each other by diffusion, wherein said gate electrode is self-aligned to an interface between said first conductivity type region and the second conductivity type region.
3. The method of claim 1 , wherein a lateral thickness of said outer dummy spacer is a sublithographic dimension, and wherein a length of said gate electrode is another sublithographic dimension.
4. The method of claim 1 , further comprising:
forming at least one planarization dielectric layer on said first conductivity type region;
planarizing said at least one planarization dielectric layer;
forming at least one replacement dielectric layer on said second conductivity type region; and
planarizing said at least one replacement dielectric layer.
5. The method of claim 4 , further comprising forming a first dielectric spacer and a second dielectric spacer, wherein said first dielectric spacer comprises a stack of a first planarization dielectric layer and a second planarization dielectric layer, and said second dielectric spacer comprises a stack of a first replacement dielectric layer and a second replacement dielectric layer, and wherein a vertical portion of said first planarization dielectric layer and a vertical portion of said first replacement dielectric layer are removed after said removing of said outer dummy spacer and prior to said forming of said gate electrode.