Semiconductor device
View Patent ↗A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of a silicon nitride film containing oxygen, and a fourth insulator formed of a silicon oxide film in this order on a main surface of a semiconductor substrate. Holes are injected into the charge-trapping layer from a gate electrode side. Accordingly, since the operations can be achieved without the penetration of the holes through the interface in contact to the channel and the first insulator, the deterioration in rewriting endurance and the charge-trapping characteristics due to the deterioration of the first insulator does not occur, and highly efficient rewriting (writing and erasing) characteristics and stable charge-trapping characteristics can be achieved.
1. A semiconductor device comprising:
a non-volatile memory element in which a gate dielectric formed on a main surface of a semiconductor substrate is used as a charge-trapping layer,
wherein the gate dielectric has a structure in which a first insulator, a second insulator, a third insulator, and a fourth insulator are laminated in this order from a side of the semiconductor substrate, and the third insulator has a bandgap larger than a bandgap of the second insulator and has an energy barrier to charges,
wherein electrons and holes are used as trapped charges for the gate dielectric used as the charge-trapping layer, the electrons are injected into the charge-trapping layer from the semiconductor substrate, and the holes are injected into the charge-trapping layer from a gate electrode formed on the gate dielectric, and
wherein the third and fourth insulators have thicknesses such that the injected holes reach the second insulator by tunneling through the fourth and third insulators, the fourth insulator being formed of a silicon oxide film.
2. The semiconductor device according to claim 1 ,
wherein the first insulator is formed of a silicon oxide film, the second insulator is formed of a silicon nitride film, the third insulator is formed of a silicon nitride film containing oxygen.
3. The semiconductor device according to claim 2 ,
wherein a composition ratio of silicon of the second insulator is larger than a composition ratio of silicon of a silicon nitride film of stoichiometric composition.
4. The semiconductor device according to claim 1 ,
wherein a dielectric constant of the third insulator is lower than a dielectric constant of the second insulator.
5. The semiconductor device according to claim 1 ,
wherein the gate electrode is made of p type polycrystalline silicon.
6. The semiconductor device according to claim 1 ,
wherein the electrons in a hot-carrier state are injected, and the holes are injected by means of tunneling.
7. The semiconductor device according to claim 1 , wherein the fourth insulator has a thickness of about 1 nm.
8. A semiconductor device comprising:
a first insulator gate field effect transistor for forming a non-volatile memory element formed on a main surface of a semiconductor substrate; and
a second insulator gate field effect transistor formed adjacent to the first insulator gate field effect transistor on the main surface of the semiconductor substrate,
wherein the first insulator gate field effect transistor includes: a first gate dielectric used as a charge-trapping layer formed on the main surface of the semiconductor substrate; and a first gate electrode formed on the first gate dielectric,
wherein the second insulator gate field effect transistor includes: a second gate dielectric formed on the main surface of the semiconductor substrate; and a second gate electrode formed on the second gate dielectric,
wherein the first gate dielectric has a structure in which a first insulator, a second insulator, a third insulator, and a fourth insulator are laminated in this order from a side of the semiconductor substrate, and the third insulator has a bandgap larger than a bandgap of the second insulator and has an energy barrier to charges,
wherein electrons and holes are used as trapped charges for the first gate dielectric used as the charge-trapping layer, the electrons are injected from a side of the semiconductor substrate, and the holes are injected from a side of the first gate electrode, and
wherein the third and fourth insulators have thicknesses such that the injected holes reach the second insulator by tunneling through the fourth and third insulators, the fourth insulator being formed of a silicon oxide film.
9. The semiconductor device according to claim 8 ,
wherein a first diffusion layer, a first channel controlled by the first gate electrode, a second channel controlled by the second gate electrode, and a second diffusion layer are arranged in an arrangement direction of the first gate electrode and the second gate electrode in the main surface of the semiconductor substrate, and
wherein a change in voltage characteristics of current flowing between the first diffusion layer and the second diffusion layer by the first gate electrode corresponds to stored data.
10. The semiconductor device according to claim 8 ,
wherein the non-volatile memory element is selected by voltage applied to the second gate electrode.
11. The semiconductor device according to claim 8 ,
wherein a high-field region is formed in a channel between the first gate electrode and the second gate electrode by the first and second insulator gate field effect transistors, and electrons are injected into the first gate dielectric by source side injection.
12. The semiconductor device according to claim 8 ,
wherein the first insulator is formed of a silicon oxide film, the second insulator is formed of a silicon nitride film, the third insulator is formed of a silicon nitride film containing oxygen.
13. The semiconductor device according to claim 8 , wherein the fourth insulator has a thickness of about 1 nm.
14. A semiconductor device comprising:
a first insulator gate field effect transistor for forming a non-volatile memory element formed on a main surface of a semiconductor substrate; and
a second insulator gate field effect transistor formed adjacent to the first insulator gate field effect transistor on the main surface of the semiconductor substrate,
wherein the first insulator gate field effect transistor includes: a first gate dielectric used as a charge-trapping layer formed on the main surface of the semiconductor substrate; and a first gate electrode formed on the first gate dielectric,
wherein the second insulator gate field effect transistor includes: a second gate dielectric formed on the main surface of the semiconductor substrate; and a second gate electrode formed on the second gate dielectric,
wherein electrons and holes are used as trapped charges, the electrons are injected from a side of the semiconductor substrate, and the holes are injected from a side of the first gate electrode,
wherein the charge-trapping layer includes a charge-trapping film and a tunnel film laminated in an upper portion of the charge-trapping layer, and
wherein the tunnel film has a thickness such that the injected holes reach the charge-trapping film by tunneling through the tunnel film, the tunnel film including a silicon oxide film.
15. The semiconductor device according to claim 14 , wherein the silicon oxide film has a thickness of about 1 nm.