IP Library Granted Patent US 7,754,565
Granted Patent B2
US 7,754,565 · App. 11/829,759 · Granted Jul 13, 2010

Manufacturing method of semiconductor device and semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,754,565
App. No.
11/829,759
Granted
Jul 13, 2010
Kind
B2
Abstract

A manufacturing method of a semiconductor device disclosed herein, comprises: forming a first member to be patterned on a semiconductor substrate; forming a second member to be patterned on the first member; forming a third member to be patterned on the second member; patterning the third member to form a first line pattern and a first connecting portion in the third member, the first line pattern having a plurality of parallel linear patterns and the first connecting portion connecting the linear patterns on at least one end side of the linear patterns of the first line pattern; etching the second member with the third member as a mask to form a second line pattern and a second connecting portion in the second member, the second line pattern being the same pattern as the first line pattern and the second connecting portion being the same pattern as the first connecting portion; removing the second connecting portion of the second member; and etching the first member with the second member as a mask.

Claims (21)

1. A manufacturing method of a semiconductor device, comprising:

forming a first member to be patterned on a semiconductor substrate;

forming a second member to be patterned on the first member;

forming a third member to be patterned on the second member;

patterning the third member to form a first line pattern and a first connecting portion in the third member, the first line pattern having a plurality of parallel linear patterns and the first connecting portion connecting the linear patterns on at least one end side of the linear patterns of the first line pattern;

etching the second member with the third member as a mask to form a second line pattern and a second connecting portion in the second member, the second line pattern being the same pattern as the first line pattern and the second connecting portion being the same pattern as the first connecting portion;

removing the second connecting portion of the second member; and

etching the first member with the second member as a mask.

2. The manufacturing method of the semiconductor device according to claim 1 , further comprising removing the third member after said etching the second member.

3. The manufacturing method of the semiconductor device according to claim 2 , wherein said removing the second connecting portion comprises:

forming a fourth member to be patterned on the second member after said removing the third member;

forming an opening in the fourth member, the opening containing the second connecting portion; and

etching the second member with the fourth member as a mask.

4. The manufacturing method of the semiconductor device according to claim 1 , wherein a part of the linear patterns of the second line pattern of the second member is also removed in said removing the second connecting portion.

5. The manufacturing method of the semiconductor device according to claim 1 , wherein the third member is a photoresist.

6. The manufacturing method of the semiconductor device according to claim 1 , wherein the second member is formed of an insulating material to be used as a mask.

7. The manufacturing method of the semiconductor device according to claim 1 , wherein the first member is formed of a conductive material.

8. The manufacturing method of the semiconductor device according to claim 1 , wherein the first line pattern is a pattern for word lines.

9. The manufacturing method of the semiconductor device according to claim 8 , wherein the word lines are for a memory cell array in a nonvolatile semiconductor memory device.

10. The manufacturing method of the semiconductor device according to claim 1 , wherein the first line pattern is a pattern for bit lines.

11. The manufacturing method of the semiconductor device according to claim 10 , wherein the bit lines are for a memory cell array in a nonvolatile semiconductor memory device.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2007
From: KINOSHITA, HIDEYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 019949/0140 →