Flat panel display and method of fabricating the same
View Patent ↗Disclosed is a flat panel display which comprises a substrate; a gate line formed on the substrate along a predetermined direction; and a gate electrode electrically connected to the gate line, and having a sheet resistance different from the gate line. With this configuration, a wiring resistance of the gate line can be lowered with minimizing the change of the process and without increasing the thickness of the gate line.
1. A method for fabricating a flat panel display, comprising:
forming a first active layer on a first transistor region of a substrate;
forming a gate line in a wiring region of the substrate;
forming a first gate electrode in the first transistor region; and
ion doping the gate line while the first gate electrode and the entire first active layer are masked.
2. The method of claim 1 , wherein ion doping comprises:
forming a photoresist pattern covering an entire surface of the first active layer and exposing the gate line; and
ion doping the gate line using the photoresist pattern as a mask.
3. The method of claim 2 , wherein the photoresist pattern is at least 5000 Å thick.
4. The method of claim 1 , wherein forming a gate line and a first gate electrode comprises:
laminating a gate insulating layer and a conductive layer on an entire surface of the substrate having the first active layer;
forming a photoresist pattern on the conductive layer covering the wiring region and a portion of the first active layer excluding a plurality of ends thereof; and
etching the conductive layer using the photoresist pattern as a mask.
5. The method of claim 4 , wherein the photoresist pattern is at least about 5000 Å thick.
6. The method of claim 4 , further comprising:
ion doping the plurality of ends using the photoresist pattern and the first gate electrode as a mask; and
removing the photoresist pattern.
7. The method of claim 1 , wherein ion doping comprises ion showering.
8. The method of claim 1 , wherein the gate line and the first gate electrode are approximately the same thickness.
9. The method of claim 1 , wherein the gate line and the first gate electrode comprise molybdenum-tungsten alloy.
10. The method of claim 1 , wherein the gate line and the first gate electrode are each between about 150 nm and about 400 nm thick.
11. The method of claim 1 , further comprising:
forming a second active layer on a second transistor region of the substrate; and
forming a second gate electrode in the second transistor region after forming the gate line and the first gate electrode.
12. The method of claim 11 , wherein forming a second gate electrode comprises:
forming a photoresist pattern on the wiring region, the first transistor region, and a portion of the second active layer excluding a plurality of ends thereof; and
etching a conductive layer using the photoresist pattern as a mask.
13. The method of claim 12 , wherein the photoresist pattern is at least about 5000 Å thick.
14. The method of claim 12 , further comprising:
ion doping the plurality of ends using the photoresist pattern and the second gate electrode as a mask; and
removing the photoresist pattern.
15. The method of claim 12 , wherein ion doping comprises:
forming a photoresist pattern covering the second gate electrode and an entire surface of the first active layer and exposing the gate line and a portion of the second active layer; and
ion doping the gate line and the portion of the second active layer using the photoresist pattern as a mask.
16. The method of claim 15 , wherein the photoresist pattern is at least 5000 Å thick.