IP Library Granted Patent US 7,638,824
Granted Patent B2
US 7,638,824 · App. 11/832,819 · Granted Dec 29, 2009

Field effect transistor having a crank-shaped multigate structure

Assignee: Mitsubishi Electric Corporation
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Quick Facts
Patent No.
US 7,638,824
App. No.
11/832,819
Granted
Dec 29, 2009
Kind
B2
Abstract

A field effect transistor includes a pair of ohmic electrodes and an n-type GaAs layer between the pair of ohmic electrodes and having recesses. Crank-shaped gate fingers are located within the recesses of the n-type GaAs layer between the pair of ohmic electrodes, and each crank-shaped gate finger includes perpendicular-extending portions and parallel-extending portions relative to the [0, 1 , 1 ] crystal orientation of the n-type GaAs layer. The portion of the n-type GaAs layer between the gate fingers continuously extends from input ends of the gate electrodes to terminal ends of the gate electrode. A non-active region is located around each perpendicular-extending portion of the gate fingers.

Claims (26)

1. A field effect transistor having a crank-shaped multigate structure, comprising:

a pair of ohmic electrodes;

a semiconductor layer located between said pair of ohmic electrodes and having a recess that has a perpendicular-extending portion and a parallel-extending portion, relative to a crystal orientation of said semiconductor layer; and

a plurality of crank-shaped gate electrodes located within said recess of said semiconductor layer, each gate electrode having a perpendicular-extending portion and a parallel-extending portion, relative to the crystal orientation of said semiconductor layer, said perpendicular-extending portion being disposed within said perpendicular-extending portion of said recess, said parallel-extending portion being disposed within said parallel-extending portion of said recess, wherein

said semiconductor layer includes a non-active region located around either said perpendicular-extending portion or said parallel-extending portion of said plurality of gate electrodes relative to the crystal orientation of said semiconductor layer, and

said semiconductor layer further includes an active region in a principal surface of said semiconductor layer, located between said plurality of gate electrodes, said active region continuously extending from input ends of said plurality of gate electrodes to terminal ends of said plurality of gate electrodes, and including a potential clamp electrode located on a surface of said active region.

2. The field effect transistor as claimed in claim 1 , wherein said non-active region is located around the one of said perpendicular-extending portion and said parallel-extending portion of said plurality of gate electrodes having a smaller width than a corresponding recess.

3. The field effect transistor as claimed in claim 1 , wherein:

said plurality of gate electrodes includes a serially connected gate finger and wire of a different material from said gate finger;

said gate finger is said gate electrode in said active region; and

said wire is said gate electrode in said non-active region.

4. The field effect transistor as claimed in claim 1 , wherein:

said semiconductor layer is n-type GaAs; and

the crystal orientation is a [0, 1 , 1 ] direction.

5. A field effect transistor having a crank-shaped multigate structure, comprising:

a pair of ohmic electrodes;

a semiconductor layer located between said pair of ohmic electrodes and including an active region and a non-active region; and

a plurality of crank-shaped gate electrodes located on said semiconductor layer, each crank-shape gate electrode having a bent portion, wherein

said active region of said semiconductor layer is disposed between said plurality of crank-shaped gate electrodes and continuously extends from input ends of said plurality of crank-shaped gate electrodes to terminal ends of said plurality of crank-shaped gate electrodes, and

said non-active region of said semiconductor layer is located under said bent portion of said plurality of crank-shaped gate electrodes.

6. The field effect transistor as claimed in claim 5 , wherein:

said semiconductor layer has a recess; and

said plurality of gate electrodes are located within said recess.

7. The field effect transistor as claimed in claim 5 , including a plurality of said non-active regions, wherein

each crank-shaped gate electrode has a plurality of substantially mutually transverse longitudinal and lateral portions, said longitudinal and lateral portions of each crank-shaped gate electrode being serially joined so that each crank-shaped gate electrode includes bent portions, and

said non-active regions are located only under said bent portions of said plurality of crank-shaped gate electrodes.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2019
From: MITSUBISHI ELECTRIC CORPORATION
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 048072/0626 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2007
From: NAKAMOTO, TAKAHIRO
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 019639/0133 →
Priority Claims (1)
JP 2007-011945 · Jan 22, 2007 · national
Continuity (1)
Related Publication 20080173907A1 · Jul 24, 2008