IP Library Granted Patent US 7,568,172
Granted Patent B2
US 7,568,172 · App. 11/833,667 · Granted Jul 28, 2009

Integration of pre-defined functionality and a graphical program in a circuit

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Quick Facts
Patent No.
US 7,568,172
App. No.
11/833,667
Granted
Jul 28, 2009
Kind
B2
Abstract

System and method for designing a circuit. At least one graphical program comprising a plurality of interconnected nodes that visually indicate functionality of the graphical program is selected in response to user input. At least one pre-defined hardware configuration program (HCP) is selected from a plurality of pre-defined HCPs in response to user input, where the selected at least one pre-defined HCP specifies a fixed functionality, including interface functionality for communicating with the at least one graphical program when implemented on the circuit. At least a portion of a netlist is generated based on the at least one graphical program and the at least one selected pre-defined HCP, where the netlist is usable to configure a circuit, wherein a first portion of the circuit implements the functionality of the graphical program and a second portion of the circuit implements the fixed functionality.

Claims (44)

1. A computer-implemented method for designing a circuit, the method comprising:

selecting at least one graphical program in response to user input, wherein the at least one graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program;

selecting at least one pre-defined hardware configuration program (HCP) from a plurality of pre-defined HCPs in response to user input, wherein the selected at least one pre-defined HCP specifies a fixed functionality, including interface functionality for communicating with the at least one graphical program when implemented on the circuit;

generating at least a portion of a netlist based on the at least one graphical program and the at least one selected pre-defined HCP;

wherein the netlist is usable to configure a circuit, wherein a first portion of the circuit implements the functionality of the graphical program and a second portion of the circuit implements the fixed functionality, and wherein the circuit comprises a programmable hardware element that includes a programmable gate array;

configuring the programmable hardware element based on the netlist to produce a configured programmable hardware element, wherein a first portion of the configured programmable hardware element implements the functionality of the at least one graphical program and a second portion of the configured programmable hardware element implements the fixed functionality;

wherein during operation of the configured programmable hardware element the first portion of the configured programmable hardware element performs the functionality of the graphical program, and the second portion of the configured programmable hardware element performs the fixed functionality.

2. The method of claim 1 , wherein the selected at least one pre-defined HCP is configured to implement an interface for a software application executing on a processor coupled to the circuit, and wherein during operation of the circuit, the interface provides an application interface for the software application.

3. The method of claim 1 , wherein the selected at least one pre-defined HCP is configured to implement an input/output (I/O) interface for an I/O element coupled to the second portion of the circuit, and wherein during operation of the circuit, the I/O interface provides an interface for the I/O element.

4. The method of claim 1 , wherein the selected at least one pre-defined HCP is configured to implement a data acquisition function, and wherein during operation of the circuit, the second portion of the circuit is operable to perform the data acquisition function to acquire data from a physical system.

5. The method of claim 1 , wherein the selected at least one pre-defined HCP is configured to implement a data analysis function, and wherein during operation of the circuit, the second portion of the circuit is operable to perform the data analysis function.

6. The method of claim 1 , wherein the at least one graphical program specifies a data acquisition function, and wherein during operation of the circuit, the first portion of the circuit is operable to perform the data acquisition function to acquire data from a physical system.

7. The method of claim 1 , wherein the at least one graphical program specifies a data analysis function, and wherein during operation of the circuit, the first portion of the circuit is operable to perform the data analysis function.

8. The method of claim 1 , wherein the at least one graphical program specifies a data analysis function, and wherein the at least one pre-defined HCP is configured to implement a data acquisition function, and wherein during operation of the circuit, the first portion of the circuit is operable to analyze data acquired by the second portion of the circuit.

9. The method of claim 1 , wherein the at least one graphical program specifies a data acquisition function, and wherein the at least one pre-defined HCP is configured to implement a data analysis function, and wherein during operation of the circuit, the second portion of the circuit is operable to analyze data acquired by the first portion of the circuit.

10. The method of claim 1 , wherein the fixed functionality comprises timing and data transfer functionality for one or more of:

the at least one graphical program functionality implemented on the first portion of the circuit;

a software application executing on a processor coupled to the circuit; or

an I/O element coupled to the second portion of the circuit.

11. The method of claim 1 , further comprising:

receiving user input configuring one or more aspects of the interface functionality for communicating with the graphical program functionality implemented on the first portion of the circuit, wherein said generating the at least a portion of the netlist is performed in accordance with said configuring the one or more aspects.

12. The method of claim 1 , wherein the at least one graphical program implements interface functionality for communicating with a host interface executing on a processor coupled to the circuit, and wherein during operation of the circuit, the first portion of the circuit is operable to communicate with the host interface.

13. The method of claim 1 , wherein the at least one graphical program implements interface functionality for communicating with an I/O element coupled to the first portion of the circuit, and wherein during operation of the circuit, the first portion of the circuit is operable to communicate with the I/O element.

14. The method of claim 1 , further comprising:

displaying a graphical user interface on a display;

wherein said selecting at least one the graphical program and said selecting the at least one pre-defined HCP comprises receiving user input adding the at least one graphical program and the at least one pre-defined HCP to a portion of the graphical user interface.

15. The method of claim 1 , further comprising:

displaying a tree structure on a display;

wherein said selecting the at least one graphical program and said selecting the at least one pre-defined HCP comprises receiving user input adding the at least one graphical program and the at least one pre-defined HCP to the tree structure.

16. The method of claim 15 , wherein said receiving user input adding the at least one graphical program and the at least one pre-defined HCP to the tree structure comprises one or more of:

receiving user input dragging and dropping respective icons representing the at least one graphical program and the at least one pre-defined HCP onto the tree structure; or

receiving user input to the tree structure invoking a menu, and receiving user input to the menu selecting the at least one graphical program and the at least one pre-defined HCP from the menu.

17. The method of claim 1 , further comprising:

displaying a graphical user interface (GUI) on a display, wherein the GUI includes an image of the circuit;

wherein said selecting the at least one graphical program and said selecting the at least one pre-defined HCP comprises receiving user input adding icons representing the at least one graphical program and the at least one pre-defined HCP to the image of the circuit.

18. The method of claim 1 , wherein the circuit comprises an application specific integrated circuit (ASIC), the method further comprising:

sending the netlist to a circuit manufacturer to manufacture the ASIC.

19. A computer accessible memory medium that stores program instructions that are executable to design a circuit, wherein the program instructions are executable by a processor to:

select at least one graphical program in response to user input, wherein the at least one graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program;

select at least one pre-defined hardware configuration program (HCP) from a plurality of pre-defined HCPs in response to user input, wherein the selected at least one pre-defined HCP specifies a fixed functionality, including interface functionality for communicating with the at least one graphical program when implemented on the circuit;

generate at least a portion of a netlist based on the at least one graphical program and the at least one selected pre-defined HCP;

wherein the netlist is usable to configure a circuit, wherein a first portion of the circuit implements the functionality of the at least one graphical program and a second portion of the circuit implements the fixed functionality, and wherein the circuit comprises a programmable hardware element that includes a programmable gate array;

configure the programmable hardware element based on the netlist to produce a configured programmable hardware element, wherein a first portion of the configured programmable hardware element implements the functionality of the at least one graphical program and a second portion of the configured programmable hardware element implements the fixed functionality;

wherein during operation of the configured programmable hardware element the first portion of the configured programmable hardware element performs the functionality of the graphical program, and the second portion of the configured programmable hardware element performs the fixed functionality.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 057280/0028) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 065231/0466 →
RELEASE OF SECURITY INTEREST IN PATENTS (REEL/FRAME 052935/0001) Recorded Oct 13, 2023
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS ADMINISTRATIVE AGENT
To: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
Reel/Frame 065653/0463 →
SECURITY INTEREST Recorded Jun 18, 2021
From: NATIONAL INSTRUMENTS CORPORATION
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 057280/0028 →
SECURITY INTEREST Recorded Jun 14, 2020
From: NATIONAL INSTRUMENTS CORPORATION; PHASE MATRIX, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 052935/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2008
From: BROWN, RYAN H.
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 021496/0349 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2007
From: BREYER, JOHN R.; ILIC, KOSTA
To: NATIONAL INSTRUMENTS CORPORATION
Reel/Frame 019657/0348 →