Circuit for switching between two clock signals independently of the frequency of the clock signals
View Patent ↗A clock switching circuit for switching between plural clock signals includes a selector for outputting a first control signal when a low speed clock is selected by a selection signal with a permission signal halted, and a second control signal when a high speed clock is selected by the selection signal with a second permission signal halted. The switching circuit includes a first stabilizer for holding the first control signal in timed with the low speed clock to output the second permission signal, and a second stabilizer for holding the second control signal in timed with the high speed clock to output the first permission signal. The switching circuit includes a first and a second gating cell circuit for latching and outputting the low speed clock and the high speed clock when the second permission signal and the first permission signal is supplied, respectively.
1. A clock switching circuit comprising:
a selector which outputs a first control signal when a first clock signal is selected by a selection signal and a first permission signal is not enabled, and which outputs a second control signal when the second clock signal is selected by the selection signal and a second permission signal is not enabled, the selection signal selecting either of the first clock signal and the second clock signal;
a first stabilizer which receives and holds the first control signal timed with the first clock signal, and which outputs the second permission signal;
a second stabilizer which receives and holds the second control signal timed with the second clock signal, and which outputs the first permission signal;
a first gating cell circuit which is operative in response to the second permission signal to latch and output the first clock signal as a first output clock signal;
a second gating cell circuit which is operative in response to the first permission signal to latch and output the second clock signal as a second output clock signal;
an output circuit which outputs the first output clock signal output from said first gating cell circuit or the second output clock signal from said second gating cell circuit as the output clock signal;
a first latch which is operative in response to the first permission signal to prevent said selector from outputting the first control signal; and
a second latch which is operative in response to the second permission signal to prevent said selector from outputting the second control signal.
2. The switching circuit in accordance with claim 1 , wherein said first stabilizer comprises a plurality of flip-flops cascaded to each other,
said second stabilizer comprising a plurality of flip-flops cascaded to each other.
3. The switching circuit in accordance with claim 1 , wherein the first clock signal is higher in frequency than the second clock signal.
4. A clock switching circuit comprising:
a selector which outputs a first control signal when a first clock signal is selected by a selection signal and a first permission signal is not enabled, and which outputs a second control signal when the second clock signal is selected by the selection signal and a second permission signal is not enabled, the selection signal selecting either of the first clock signal and the second clock signal;
a first stabilizer connected to said selector to output the second permission signal responsive to the first control signal as timed with the first clock signal;
a second stabilizer connected to said selector to output the first permission signal responsive to the second control signal as timed with the second clock signal;
a first gating cell circuit connected to said first stabilizer to output the first clock signal in response to the second permission signal;
a second gating cell circuit connected to said second stabilizer to output the second clock signal in response to the first permission signal;
an output circuit connected to said first and second gating cell circuits to output the first clock signal or the second clock signal as an output clock signal from said clock switching circuit:
a first latch, connected between said first stabilizer and said selector, and responsive to the second permission signal to prevent said selector from outputting the second control signal; and
a second latch, connected between said second stabilizer and said selector, and responsive to the first permission signal to prevent said selector from outputting the first control signal.
5. The switching circuit in accordance with claim 4 , wherein said first stabilizer comprises a plurality of flip-flops cascaded to each other,
said second stabilizer comprising a plurality of flip-flops cascaded to each other.
6. The switching circuit in accordance with claim 4 , wherein the first clock signal is higher in frequency than the second clock signal.