IP Library Granted Patent US 7,359,570
Granted Patent B2
US 7,359,570 · App. 11/835,243 · Granted Apr 15, 2008

Method of reducing a blocking artifact when coding moving picture

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,359,570
App. No.
11/835,243
Granted
Apr 15, 2008
Kind
B2
Abstract

A method of coding a moving picture is provided that reduces blocking artifacts. The method can include defining a plurality of defining pixels S 0 , S 1 , and S 2 , which are centered around a block boundary. If a default mode is selected then frequency information of the surroundings of the block boundary is obtained. A magnitude of a discontinuous component in a frequency domain belonging to the block boundary is adjusted based on a magnitude of a corresponding discontinuous component selected from a pixel contained entirely within a block adjacent the block boundary. The frequency domain adjustment is then applied to a spatial domain. Or, a DC offset mode can be selected to reduce blocking artifacts in smooth regions where there is little motion.

Claims (85)

1. A method of reducing a blocking artifact appearing when coding a picture, comprising:

dividing the picture into blocks that each include multiple pixels, a first pixel of a first block being separated from a second pixel of a neighboring second block by a block boundary;

selecting a correction mode from at least a default mode and a direct current (DC) offset mode based on whether a region adjacent to the block boundary is smooth; and

adjusting the first pixel of the first block based upon the second pixel of the second block when the default mode is selected.

2. The method of claim 1 ,

wherein adjusting the first pixel further comprises replacing a pixel value v 3 of the first pixel with a value v 3 ′,

wherein the value v 3 ′ is expressed as:

v 3 ′=v 3 −d,

wherein d is expressed as:

d

=

CLIP

(

c

2

(

a

3

,

0

-

a

3

,

0

)

//

c

3

,

0

,

(

v

3

-

v

4

)

2

)

*

δ

(

a

3

,

0

<

QP

)

,

wherein α 3,0 ′ is expressed as:

α 3,0 ′=SIGN(α 3,0 )*MIN(|α 3,0 |,|α 3,1 |,|α 3,2 |),

wherein QP represents a quantization parameter of the second block, c 2 and c 3 represent DCT kernel coefficients, and v 4 represents a pixel value of the second pixel.

3. The method of claim 2 , wherein if, and wherein

δ(|α 3,0 |<QP )=0 |α 3,0 |≧QP δ (|α 3,0 |<QP )=1 if |α 3,0 |<QP.

4. The method of claim 2 , wherein c 2 is an integer and c 3 is a multiple of 2.

5. The method of claim 4 , wherein c 2 =5 and c 3 =8.

6. The method of claim 1 , further comprising applying the adjusting operation to a spatial domain of the first pixel.

7. The method of claim 1 , wherein the block boundary is a vertical or horizontal block boundary.

8. The method of claim 1 , further comprising adjusting the second pixel based upon frequency information of the first pixel when the default mode is selected.

9. The method of claim 1 , wherein a magnitude of the adjusting operation is constrained to be no greater than half of the difference between a value of the first pixel and a value of the second pixel, using a clipping function.

10. The method of claim 1 , wherein a magnitude of the adjusting operation is based upon a simple inner product of a DCT kernel and the first and second pixels.

11. The method of claim 1 , wherein a magnitude of the adjusting operation is based upon a minimum magnitude of frequency information of the first and second pixels.

12. The method of claim 1 , wherein a magnitude of the adjusting operation is based upon frequency information of the first pixel and the second pixel when the default mode is selected.

13. The method of claim 1 , further comprising obtaining the frequency information for the second pixel, wherein the first pixel is adjusted if a magnitude of the blocking artifact is less than a quantization parameter of the second block.

14. The method of claim 1 , wherein the first pixel is adjusted in a first way when the default mode is selected, the method further comprising modifying the first pixel in a second, different way when the DC offset mode is selected.

15. The method of claim 1 ,

wherein the default mode is selected if the region adjacent to the block boundary is smooth, and

wherein the DC offset mode is selected if the region adjacent to the block boundary is not smooth.

16. An apparatus for reducing a blocking artifact appearing when coding a picture, the apparatus comprising a blocking filter configured to:

divide the picture into blocks that each include multiple pixels, a first pixel of a first block being separated from a second pixel of a neighboring second block by a block boundary;

select a correction mode from at least a default mode and a direct current (DC) offset mode based on whether a region adjacent to the block boundary is smooth; and

adjust the first pixel of the first block based upon the second pixel of the second block when the default mode is selected.

17. An apparatus for reducing a blocking artifact appearing when coding a picture, comprising:

means for dividing the picture into blocks that each include multiple pixels, a first pixel of a first block being separated from a second pixel of a neighboring second block by a block boundary;

means for selecting a correction mode from at least a default mode and a direct current (DC) offset mode based on whether a region adjacent to the block boundary is smooth; and

means for adjusting the first pixel of the first block based upon the second pixel of the second block when the default mode is selected.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2013
From: VIDEO ENHANCEMENT SOLUTIONS LLC
To: LG ELECTRONICS INC.
Reel/Frame 031744/0542 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2009
From: ACACIA PATENT ACQUISITION LLC
To: VIDEO ENHANCEMENT SOLUTIONS LLC
Reel/Frame 023494/0900 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2009
From: LG ELECTRONICS
To: ANPA INC.
Reel/Frame 023454/0460 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2009
From: ANPA INC.
To: ACACIA PATENT ACQUISITIONS LLC
Reel/Frame 023454/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2007
From: KIM, HYUN MUN; RA, JONG BEOM; KIM, SUNG DEUK; LEE, YOUNG SU
To: LG ELECTRONICS INC.
Reel/Frame 019829/0257 →