IP Library Patent Application 11835393
Patent Application
App. No. 11/835,393

Computer System For Reading And Writing Data

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Quick Facts
Patent No.
US None
App. No.
11/835,393
Abstract

A system for reading and writing data has a fixed or removable data storage device having a non-volatile memory for storing data, a non-volatile memory controller, a peripheral component interface ported to the controller, and a host computing appliance having a peripheral component interface connector and a host system bus connected to a printed circuit board. In one embodiment, the removable data storage device plugs into the peripheral component interface connector allowing a direct data channel to a main bus of the computing appliance for reading from and writing to the non-volatile memory on the device.

Claims (16)

1 . A system for reading and writing data comprising:

a fixed or removable data storage device having a non-volatile memory for storing data;

a non-volatile memory controller;

a peripheral component interface ported to the controller; and

a host computing appliance having a peripheral component interface connector and a host system bus connected to a printed circuit board;

characterized in that the removable data storage device plugs into the peripheral component interface connector allowing a direct data channel to a main bus of the computing appliance for reading from and writing to the non-volatile memory on the device.

2 . The system of claim 1 , wherein the non-volatile memory is one or a combination of a non-volatile random access memory, or a flash memory.

3 . The system of claim 1 further including disk controller registers and or bus controller registers within the peripheral component interface.

4 . The system of claims 1 and 3 , wherein the non-volatile memory controller is a dedicated flash memory controller.

5 . The system of claims 1 and 3 , wherein the non-volatile memory controller is a dedicated parallel flash controller.

6 . The system of claim 3 , wherein the disk controller registers are advanced technology attachment registers and the bus controller registers are universal serial bus registers.

7 . The system of claim 4 , wherein the flash controller is a series-parallel flash controller.

8 . The system of claim 7 , further including a random access memory controller ported for communication to the series-parallel flash controller and a random access memory chip connected to the random access memory controller.

9 . The system of claim 8 , wherein the random access memory is used to cache data written to and from flash memory.

10 . The system of claims 1 , 4 , and 6 , wherein the host-computing appliance is one of a desktop or a laptop computer.

11 . The system of claim 9 , further including one or more flash address management tables residing in memory connected to the random access memory controller.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2012
From: DATARAM CORPORATION
To: PHAN TIA GROUP PTE. LLC
Reel/Frame 028295/0763 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE RECEIVING PARTY FROM DATARAM, INC. TO DATARAM CORPORATION PREVIOUSLY RECORDED ON REEL 021149 FRAME 0175. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 31, 2012
From: CENATEK, INC.
To: DATARAM CORPORATION
Reel/Frame 028306/0931 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2008
From: CENATEK, INC.
To: DATARAM, INC.
Reel/Frame 021149/0175 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2007
From: CAULKINS, JASON
To: CENATEK
Reel/Frame 019822/0735 →