IP Library Granted Patent US 8,225,022
Granted Patent B2
US 8,225,022 · App. 11/835,395 · Granted Jul 17, 2012

Methods for eliminating intermediate bussing and bridging requirements between a solid state memory device with PCI controller and a main system bus

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Quick Facts
Patent No.
US 8,225,022
App. No.
11/835,395
Granted
Jul 17, 2012
Kind
B2
Abstract

A method is provided for enabling electronic representation of a removable or fixed data storage device having a non-volatile memory as an operating system-standard disk directly accessible to a main bus of a computing appliance having a peripheral component interface connector and a motherboard. The method includes the acts (a) providing a peripheral component interface ported to a memory controller on the device, the memory controller for controlling host access to the non-volatile memory, (b) providing disk control registers and or bus control registers including appropriate disk and or bus protocols and commands in the peripheral component interface on the device, and (c) connecting the device to the peripheral component interface connector of the computing appliance.

Claims (17)

1. A method for enabling electronic representation of a removable or fixed data storage device comprising flash memory units as an operating system standard disk directly accessible to a main bus of a computing appliance having a peripheral component interface connector and a motherboard, comprising the steps of:

(a) connecting the flash memory units together both in series and in parallel;

(b) providing an integrated controller directly on the device, the integrated controller comprising a peripheral component interface (PCI) ported to a series-parallel PCIFLASH memory controller on the device, the memory controller enabled to control host access to the flash memory units either in series, in parallel, or both;

(c) providing disk control registers and or bus control registers including appropriate disk and or bus protocols and commands in the peripheral component interface on the device; and

(d) connecting the device carrying the integrated controller, including the PCI, to the peripheral component interface connector of the computing appliance wherein the computing appliance immediately recognizes the device as a disk without input from a disk controller, disk controller interface, disk channel, USB controller/channel interface and actual hard disk channel interface.

2. The method of claim 1 wherein in step (b), the peripheral component interface and the memory controller are packaged as a system interface controller installable to a card supporting the flash memory units.

3. The method of claim 1 wherein in step (c), the disk controller registers are provided in the form of advanced technology attachment controller registers.

4. The method of claim 1 wherein in step (c), the bus controller registers are provided in the form of universal serial bus controller registers.

5. The method of claim 1 wherein in step (d), the peripheral component interface connector is presented in a standard peripheral component interface slot on the computing appliance.

6. The method of claim 1 wherein in step (d), the peripheral component interface connector is presented on the motherboard of the computing appliance, the device fixedly wired to the motherboard.

7. A method for accelerating reading and writing of data from a removable or fixed data storage device comprising flash memory units connected together both in series and in parallel communication and a system interface controller, the system interface controller including a series-parallel flash memory controller and a peripheral component interface (PCI) with disk and or bus controller registers, including the acts of:

(a) providing a random access memory controller to the system interface controller, which includes a PCI, and porting it to the flash memory controller;

(b) providing a random access memory chip to the system interface controller and connecting the chip to the random access memory controller;

(c) providing flash memory address translation tables in the random access memory; and

(d) using the random access memory as a data cache for read and write operations performed by a computing appliance wherein, upon connection between the device and the computing appliance, the computing appliance immediately recognizes the device as a disk without input from a disk controller, disk controller interface, disk channel, USB controller/channel interface and actual hard disk channel interface.

8. The method of claim 7 , wherein the disk controller registers are provided in the form of advanced technology attachment controller registers.

9. The method of claim 7 , wherein the bus controller register are provided in the form of universal serial bus controller registers.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2015
From: INTELLECTUAL VENTURES ASSETS 11 LLC ·
To: SK HYNIX INC.
Reel/Frame 034925/0802 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2014
From: PHAN TIA GROUP PTE. LLC
To: INTELLECTUAL VENTURES ASSETS 11 LLC
Reel/Frame 034571/0557 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2012
From: DATARAM CORPORATION
To: PHAN TIA GROUP PTE. LLC
Reel/Frame 028295/0763 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE RECEIVING PARTY FROM DATARAM, INC. TO DATARAM CORPORATION PREVIOUSLY RECORDED ON REEL 021149 FRAME 0175. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 31, 2012
From: CENATEK, INC.
To: DATARAM CORPORATION
Reel/Frame 028306/0931 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2008
From: CENATEK, INC.
To: DATARAM, INC.
Reel/Frame 021149/0175 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2007
From: CAULKINS, JASON
To: CENATEK
Reel/Frame 019822/0767 →