Method for reducing body diode conduction in NMOS synchronous rectifiers

1. A method for operating a switching regulator, the switching regulator comprising a high-side switch and a low-side switch, the method comprising:

controlling the high-side switch to be substantially depleted during a first operational phase and to be substantially enhanced during a second operational phase;

controlling the low-side switch to be substantially enhanced during the first operational phase and to provide a regulated drain-to-source current during the second operational phase;

enabling a current mirror to generate a gate voltage for the low-side switch during the second operational phase;

using, a drain voltage of a diode-connected N-channel MOSFET as the gate voltage of the low-side switch, a current source supplying the gate and drain of the N-channel MOSFET; and

during transitions between the second and first operational phases, controlling the low-side switch to momentarily decrease the regulated drain-to-source current and providing an AC coupling between a voltage used to drive the high-side switch and the gate of the N-channel MOSEFT to momentarily decrease the low-side voltage.

2. The method of claim 1 further comprising controlling an on-time of the high-side switch and an on-time of the low-side switch with a pulse width modulation signal.

3. The method of claim 2 further comprising ensuring that the high-side switch and the low-side switch are not simultaneously ON.

4. The method of claim 2 comprising passing a voltage at a common node between the high-side and low-side switches through an inductor to generate an output voltage.

5. The method of claim 4 comprising using the output voltage to control the pulse width modulation signal.

6. The method of claim 1 further comprising controlling an on-time of the high-side switch and an on-time of the low-side switch with a pulse frequency modulation signal.

7. The method of claim 6 further comprising ensuring that the high-side switch and the low-side switch are not simultaneously ON.

8. The method of claim 6 comprising passing a voltage at a common node between the high-side and low-side switches through an inductor to generate an output voltage.

9. The method of claim 8 comprising using the output voltage to control the pulse frequency modulation signal.

10. A switching regulator comprising:

a high-side switch;

a low-side switch;

a high-side driver circuit configured to control the high-side switch to be substantially depleted during a first operational phase and to be substantially enhanced during a second operational phase;

a low-side driver circuit that controls the low-side switch to be substantially enhanced during the first operational phase and to provide a regulated drain-to-source current during the second operational phase;

a current mirror that is enabled during the second operational phase to generate a gate voltage for the low-side switch, the current mirror comprising a diode connected N-channel MOSFET having its drain connected to supply the gate voltage of the low-side switch and a current source to supply the gate and drain of the N-channel MOSFET;

a coupling circuit, that momentarily decreases the regulated drain-to-source current during transitions between the second and first operational phases; and

an AC coupling circuit connected between a voltage used to drive the high-side switch and the gate of the N-channel MOSFET to momentarily decrease the low-side drive voltage during transitions between the second and first operational phases.

11. The switching regulator of claim 10 further comprising a circuit for generating a pulse width modulation signal coupled to the high-side driver circuit and to the low-side driver circuit.

12. The switching regulator of claim 11 further comprising a break-before-make circuit connected between the circuit for generating, a pulse width modulation signal and each of the high-side driver circuit and the low-side driver circuit.

13. The switching regulator of claim 11 further comprising, an inductor connected between a common node between the high-side and low-side switches and an output voltage terminal.

14. The switching regulator of claim 13 further comprising a filter capacitor connected between the output voltage terminal and ground.

15. The switching regulator of claim 14 further comprising a feedback circuit connected between the output voltage terminal and an input terminal of the circuit for generating a pulse width modulation signal.

16. The switching regulator of claim 10 further comprising a circuit for generating, a pulse frequency modulation signal coupled to the high-side driver circuit and to the low-side driver circuit.

17. The switching regulator of claim 16 further comprising a break-before-make circuit connected between the circuit fir generating a pulse frequency modulation signal and each of the high-side driver circuit and the low-side driver circuit.

18. The switching regulator of claim 16 further comprising an inductor connected between a common node between the high-side and low-side switches and an output voltage terminal.

19. The switching regulator of claim 18 further comprising a filter capacitor connected between the output voltage terminal and ground.

20. The switching regulator of claim 19 further comprising a feedback circuit connected between the output voltage terminal and an input terminal of the circuit for generating a pulse frequency modulation signal.