Bipolar method and structure having improved BVCEO/RCS trade-off made with depletable collector columns
View Patent ↗In accordance with the invention, there are various methods of making an integrated circuit comprising a bipolar transistor. According to an embodiment of the invention, the bipolar transistor can comprise a substrate, a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity, and a collector contact in electrical contact with the collector. The bipolar transistor can also comprise a heavily doped buried layer below the collector, a base in electrical contact with a base contact, wherein the base is doped to a net second conductivity type and wherein the base spans a portion of the plurality of alternating doped regions, and an emitter disposed within the base, the emitter doped to a net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×10 12 cm −2 .
1. An integrated circuit comprising a bipolar transistor comprising:
a substrate;
a collector comprising a plurality of alternating doped regions, wherein the plurality of alternating doped regions alternate in a lateral direction from a net first conductivity to a net second conductivity;
a collector contact in electrical contact with the collector;
a heavily doped buried layer below the collector;
a base in electrical contact with a base contact, wherein the base is doped to the net second conductivity type and wherein-the base spans a portion of the plurality of alternating doped regions; and
an emitter disposed totally within the base, the emitter doped to the net first conductivity, wherein a portion of the alternating doped region under the emitter is doped to a concentration of less than about 3×10 12 cm −2 in the lateral direction.
2. The integrated circuit comprising a bipolar transistor according to claim 1 , wherein the portion of the alternating doped region under the emitter is doped to a concentration of less than about 2×10 12 cm −2 in a lateral direction.
3. The integrated circuit comprising a bipolar transistor according to claim 1 , wherein a portion of the alternating doped regions disposed beneath the emitter is doped to a net first conductivity type.
4. The integrated circuit comprising a bipolar transistor according to claim 3 , wherein a width of the doped region disposed beneath the emitter is substantially the same as a width of the emitter.
5. The integrated circuit comprising a bipolar transistor according to claim 3 , wherein the doped region disposed beneath the emitter extends from the base to the more heavily doped buried layer.
6. The integrated circuit comprising a bipolar transistor according to claim 5 , wherein the length, as defined from the base to the buried layer, of the alternating doped region under the emitter is defined by BV CEO /E crit .
7. The integrated circuit comprising a bipolar transistor according to claim 1 further comprising:
an electrical sinker in electrical contact with the collector contact and in electrical contact with the more heavily doped buried layer.
8. The integrated circuit comprising a bipolar transistor according to claim 3 farther comprising:
at least one doped second region disposed adjacent to the doped region disposed under the emitter, wherein the at least one doped second region is doped to a net second conductivity type.
9. The integrated circuit comprising a bipolar transistor according to claim 8 , wherein the doped region disposed beneath the emitter depletes at a reverse bias collector base voltage of magnitude less than an absolute value of BV CEO .
10. The integrated circuit comprising a bipolar transistor according to claim 8 , wherein the doped second regions disposed adjacent to the doped region disposed beneath the emitter depletes under a reverse bias collector voltage less than BV CEO .
11. The integrated circuit comprising a bipolar transistor according to claim 1 , further comprising a second bipolar transistor, wherein the bipolar transistor has a breakdown voltage greater than the second bipolar transistor.
12. The integrated circuit comprising a bipolar transistor according to claim 8 , wherein the doped second regions disposed adjacent to the doped region disposed beneath the emitter do not totally deplete at a magnitude of collector base voltage less than the magnitude of the BVCEO breakdown voltage.
13. The integrated circuit comprising a bipolar transistor according to claim 1 , wherein an integral across the width of the doped region under the emitter has a value of less than about 3E12 ions/cm 2 .
14. The integrated circuit comprising a bipolar transistor according to claim 1 , wherein the portion of doped region under the emitter is self aligned to the emitter.
15. An integrated circuit comprising a bipolar transistor comprising:
a substrate;
a base formed in the substrate;
a collector comprising a doped first region doped to a net first conductivity disposed under the base, to cover the base and doped second regions doped to a net second conductivity disposed on opposite sides of the doped first region; wherein the base is doped to the net second conductivity type;
a collector contact in electrical contact with the collector;
a more heavily doped layer buried below the doped first region and the doped second regions; and
an emitter doped to the net first conductivity disposed within the base, wherein the doped region disposed beneath the emitter depletes at a reverse bias collector base voltage of magnitude less than an absolute value of BV CEO .
16. The integrated circuit comprising a bipolar transistor according to claim 15 , wherein the doped second regions disposed adjacent to the doped first region do not totally deplete under reverse bias of the collector to base junction.
17. The integrated circuit comprising a bipolar transistor according to claim 15 , wherein the bipolar transistor is an NPN bipolar transistor comprising a BV CEO of at least 69 Volts.
18. The integrated circuit comprising a bipolar transistor according to claim 15 , wherein the bipolar transistor is a PNP bipolar transistor comprising a BV CEO of at least 82 Volts.
19. The integrated circuit comprising a bipolar transistor according to claim 15 , wherein the bipolar transistor is an NPN bipolar transistor, and wherein the collector is doped with at least about 2×10 15 atoms/cm 3 .
20. The integrated circuit comprising a bipolar transistor according to claim 15 , wherein the bipolar transistor is an NPN bipolar transistor, and wherein first doped region has a length of about 4 μm to about 6 μm, and further wherein the first doped region has a width of about 7 μm to about 9 μm.
21. The integrated circuit comprising a bipolar transistor according to claim 15 , wherein the bipolar transistor is a PNP bipolar transistor, and wherein the collector is doped with at least about 4×10 15 atoms/cm 3 .
22. The integrated circuit comprising a bipolar transistor according to claim 15 , wherein the bipolar transistor is a PNP bipolar transistor, and wherein first doped region has a length of about 3 μm to about 5 μm, and further wherein the first doped region has a width of about 3 μm to about 5 μm.
23. The integrated circuit comprising a bipolar transistor according to claim 18 , further comprising:
a PNP bipolar transistor comprising a BV CEO of at least 82 Volts.
24. The integrated circuit comprising a bipolar transistor according to claim 15 , wherein the doped region disposed beneath the emitter is self aligned to the emitter.