Method of acceptance for semiconductor devices

1. A method of accepting semiconductor chips using on-chip parametric measurements, the method comprising:

determining an on-chip parametric measurement structure for each parameter in a set of parametric acceptance criteria;

including an on-chip parametric measurement macro in a design of each semiconductor chip for each identified on-chip parametric measurement structure;

testing each on-chip parametric measurement macro to determine compliance of the semiconductor chip to the set of parametric acceptance criteria; and

validating the compliance to the set of parametric acceptance criteria.

2. The method of claim 1 wherein the set of parametric acceptance criteria is established by

identifying parametric acceptance criteria for each semiconductor chip; and

documenting the identified parametric acceptance criteria.

3. The method of claim 1 wherein including the on-chip parametric measurement macro comprises:

including a scaling parametric measurement (SPM) macro in the design of the semiconductor chip for each identified on-chip parametric measurement structure.

4. The method of claim 1 wherein testing each on-chip parameter measurement macro comprises:

testing each on-chip parametric measurement macro to determine compliance of the semiconductor chip to the set of parametric acceptance criteria in a wafer-level test.

5. The method of claim 1 wherein testing each on-chip parameter measurement macro comprises:

testing each on-chip parametric measurement macro to determine compliance of the semiconductor chip to the set of parametric acceptance criteria in a module-level test.

6. The method of claim 1 wherein validating the compliance is performed by a designer of the semiconductor chip.

7. The method of claim 1 further comprising:

using the on-chip parametric measurement macros to debug a design issue.