Printed circuit board design system and method
View Patent ↗A printed circuit board (PCB) design system and method allows for PCB layouts that can be manufactured using a PCB manufacturing technology selected from multiple PCB manufacturing technologies with minimal or no modification to the PCB layout. In accordance with the exemplary embodiment, the PCB layout is designed to meet all design rules of a High Density Interconnect (HDI) manufacturing technology while minimizing requirements for layout changes when the PCB is manufactured using an Interstitial Via Hole (IVH) manufacturing technology. An IVH PCB includes a plurality of vias positioned within reserved via areas that form connections between at least some conductive elements on the board layers. The conductive elements and the plurality of vias form a layout such that a majority of reserved via areas, of all of the reserved via areas on the printed circuit board, are adequate to accommodate mechanically drilled vias manufactured with the HDI manufacturing technology.
1. A printed circuit board comprising:
a plurality of dielectric layers comprising a plurality of inner dielectric layers positioned between a plurality of outer dielectric layers;
a via positioned within a first reserved via area within at least one of the inner dielectric layers, wherein the first reserved via area meets all pertinent design rules of both a first manufacturing technology and a second manufacturing technology; and
a second reserved via area, through which the via does not extend, formed at a via location of the via and within at least one inner dielectric layer above or below the inner dielectric layer in which the via is located, wherein the second reserved via area meets all pertinent design rules of the second manufacturing technology.
2. The printed circuit board of claim 1 , wherein the first manufacturing technology is an Interstitial Via Hole (IVH) manufacturing technology and the second manufacturing technology is a High Density Interconnect (HDI) manufacturing technology.
3. The printed circuit board of claim 1 , wherein the second reserved via area comprises one or more reserved via areas, wherein one of the one or more reserved via areas is disposed within every inner dielectric layer in which the via is not located, each of the one or more reserved via areas located at the via location.
4. The printed circuit board of claim 3 , wherein the second reserved via area is clear of traces and other components.
5. The printed circuit board of claim 1 , wherein the second reserved via area has a size that is substantially the same as a size of the first reserved via area.
6. The printed circuit board of claim 1 , wherein the second reserved via area has a shape that is substantially the same as a shape of the first reserved via area.