IP Library Granted Patent US 7,847,797
Granted Patent B2
US 7,847,797 · App. 11/837,589 · Granted Dec 7, 2010

Drive circuit and drive device for liquid crystal display

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Quick Facts
Patent No.
US 7,847,797
App. No.
11/837,589
Granted
Dec 7, 2010
Kind
B2
Abstract

The present invention provides a drive circuit suitable for use in a liquid crystal display, comprising an op amp which has an inversion input, a non-inversion input and a first output and of which the inversion input and the first output are connected to each other; a first PMOS transistor having a gate to which a node for the non-inversion input of the op amp is connected, and a source to which a node for the output of the op amp is connected; a first NMOS transistor having a gate to which a drain of the first PMOS transistor is connected, a drain to which the node for the output of the op amp is connected, and a source connected to ground; and a second NMOS transistor having a gate supplied with a predetermined first voltage, a drain to which the drain of the first PMOS transistor is connected, and a source connected to ground.

Claims (55)

1. A drive circuit suitable for use in a liquid crystal display, comprising:

an op amp which has an inversion input, a non-inversion input and a first output and of which the inversion input and the first output are connected to each other;

a first PMOS transistor having a gate to which a node for the non-inversion input of the op amp is connected, and a source to which a node for the output of the op amp is connected;

a first NMOS transistor having a gate to which a drain of the first PMOS transistor is connected, a drain to which the node for the output of the op amp is connected, and a source connected to ground; and

a second NMOS transistor having a gate supplied with a predetermined first voltage, a drain to which the drain of the first PMOS transistor is connected, and a source connected to ground.

2. The drive circuit according to claim 1 , further including:

a third NMOS transistor having a gate to which the node for the non-inversion input of the op amp is connected, and a source to which the node for the output of the op amp is connected;

a second PMOS transistor having a gate to which a drain of the third NMOS transistor is connected, a drain to which the node for the output of the op amp is connected, and a source connected to a power supply; and

a third PMOS transistor having a gate supplied with a predetermined second voltage, a drain to which the drain of the third NMOS transistor is connected, and a source connected to the power supply.

3. A drive circuit suitable for use in a liquid crystal display, comprising:

an op amp which has an inversion input, a non-inversion input and a first output and of which the inversion input and the first output are connected to each other;

a first PMOS transistor turned on/off by detecting a difference in potential between the first output of the op amp and the non-inversion input thereof;

a first NMOS transistor turned on/off according to the turning on/off of the first PMOS transistor and operated so as to cancel out the difference in potential between the first output and the non-inversion input; and

a second NMOS transistor which is connected in series between the first PMOS transistor and ground and has a gate supplied with a voltage greater than or equal to a threshold value thereof.

4. The drive circuit according to claim 3 , further including:

a third NMOS transistor turned on/off by detecting the difference in potential between the first output of the op amp and the non-inversion input thereof;

a second PMOS transistor turned on/off according to the turning on/off of the third NMOS transistor and operated so as to cancel out the difference in potential between the first output and the non-inversion input; and

a third PMOS transistor which is connected in series between the third NMOS transistor and a power supply and has a gate supplied with a voltage less than or equal to a threshold value thereof.

5. A drive circuit suitable for use in a liquid crystal display, comprising:

an op amp which has an inversion input, a non-inversion input and a first output and of which the inversion input and the first output are connected to each other;

a third NMOS transistor having a gate to which a node for the non-inversion input of the op amp is connected, and a source to which a node for the output of the op amp is connected;

a second PMOS transistor having a gate to which a drain of the third NMOS transistor is connected, a drain to which the node for the output of the op amp is connected, and a source connected to a power supply; and

a third PMOS transistor having a gate supplied with a predetermined second voltage, a drain to which the drain of the third NMOS transistor is connected, and a source connected to the power supply.

6. A drive circuit suitable for use in a liquid crystal display, comprising:

an op amp which has an inversion input, a non-inversion input and a first output and of which the inversion input and the first output are connected to each other;

a third NMOS transistor turned on/off by detecting a difference in potential between the first output of the op amp and the non-inversion input thereof;

a second PMOS transistor turned on/off according to the turning on/off of the third NMOS transistor and operated so as to cancel out the difference in potential between the first output and the non-inversion input; and

a third PMOS transistor which is connected in series between the third NMOS transistor and a power supply and has a gate supplied with a voltage less than or equal to a threshold value thereof.

7. A drive device suitable for use in a liquid crystal display, including a plurality of drive circuits each comprising:

an op amp which has an inversion input, a non-inversion input and a first output and of which the inversion input and the first output are connected to each other;

a first PMOS transistor having a gate to which a node for the non-inversion input of the op amp is connected, and a source to which a node for the output of the op amp is connected;

a first NMOS transistor having a gate to which a drain of the first PMOS transistor is connected, a drain to which the node for the output of the op amp is connected, and a source connected to ground;

a second NMOS transistor having a gate supplied with a predetermined first voltage, a drain to which the drain of the first PMOS transistor is connected, and a source connected to ground;

a third NMOS transistor having a gate to which the node for the non-inversion input of the op amp is connected, and a source to which the node for the output of the op amp is connected;

a second PMOS transistor having a gate to which a drain of the third NMOS transistor is connected, a drain to which the node for the output of the op amp is connected, and a source connected to a power supply; and

a third PMOS transistor having a gate supplied with a predetermined second voltage, a drain to which the drain of the third NMOS transistor is connected, and a source connected to the power supply,

wherein the drive device has output pads corresponding to the drive circuits respectively, and

wherein each of the drive circuits includes first switch means provided between the node for the output of the op amp and the corresponding output pad, and second switch means provided between nodes lying between the first switch means of the drive circuit and the output pad.

8. A drive circuit suitable for use in a liquid crystal display, comprising:

an op amp which has an inversion input, a non-inversion input, a first output and a control terminal and of which the inversion input and the first output are connected to each other, and which switches, according to a control signal inputted to the control terminal, whether an output corresponding to the non-inversion input is outputted/non-outputted to the first output;

third switch means connected to an output node of the op amp and turned on/off by the control signal;

fourth switch means connected to the output node of the op amp and turned on/off by the control signal;

a first PMOS transistor having a gate to which a node for the non-inversion input of the op amp is connected, and a source to which the output node of the op amp is connected via the third switch means;

a first NMOS transistor having a gate to which a drain of the first PMOS transistor is connected, a drain to which the output node of the op amp is connected, and a source connected to ground;

a second NMOS transistor having a gate supplied with a predetermined first voltage, a drain to which the drain of the first PMOS transistor is connected, and a source connected to ground;

a third NMOS transistor having a gate to which the node for the non-inversion input of the op amp is connected, and a source to which the output node of the op amp is connected via the fourth switch means;

a second PMOS transistor having a gate to which a drain of the third NMOS transistor is connected, a drain to which the output node of the op amp is connected, and a source connected to a power supply; and

a third PMOS transistor having a gate supplied with a predetermined second voltage, a drain to which the drain of the third NMOS transistor is connected, and a source connected to the power supply.

9. A drive device suitable for use in a liquid crystal display, including a plurality of the drive circuits each defined as claimed in claim 8 ,

wherein the drive device has output pads corresponding to the drive circuits respectively, and

wherein each of the drive circuits includes first switch means provided between the node for the output of the op amp and the corresponding output pad, and second switch means provided between nodes lying between the first switch means of the drive circuit and the output pad.

10. A drive device suitable for use in a liquid crystal display, comprising:

a plurality of digital/analog converters each of which selects and outputs a predetermined analog voltage from a gradation voltage generating circuit according to input data; and

a plurality of output circuits each of which inputs an output of said each digital/analog converter therein and outputs a drive voltage,

wherein each of the output circuits has a first transistor which compares the output of the digital/analog converter and the output of the output circuit and is turned on when a predetermined different in potential occurs between the output of the digital/analog converter and the output of the output circuit, and a second transistor turned on so as to cause the output of the output circuit to approach the potential of the output of the digital/analog converter according to the first transistor.

Assignments (3)
CHANGE OF NAME Recorded Mar 21, 2014
From: OKI SEMICONDUCTOR CO., LTD
To: LAPIS SEMICONDUCTOR CO., LTD.
Reel/Frame 032495/0483 →
CHANGE OF NAME Recorded Mar 19, 2009
From: OKI ELECTRIC INDUSTRY CO., LTD.
To: OKI SEMICONDUCTOR CO., LTD.
Reel/Frame 022443/0893 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2008
From: YAMAZAKI, KOJI
To: OKI ELECTRIC INDUSTRY CO., LTD.
Reel/Frame 021934/0898 →