Test data compression method for system-on-chip using linear-feedback shift register reseeding
View Patent ↗A method includes obtaining an equivalent core of multiple cores in a System-on-Chip circuit, and applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core.
1. A method comprising the steps of:
obtaining an equivalent core of multiple cores in a System-on-Chip circuit; and
applying linear-feedback shift register LFSR reseeding for compressing test data of the equivalent core, wherein testing time of the equivalent core is optimized by ensuring that for any scan slice of the equivalent core, the number of care bits does not exceed a user defined parameter such that the LFSR can guarantee to encode at least one scan slice.
2. The method of claim 1 , wherein the step of obtaining comprises having more care bits per slice scan for the equivalent core for any of each individual multiple core.
3. The method of claim 1 , wherein the step of obtaining comprises having a care-bit distribution over scan slices which is more flat for the equivalent core than for any of each individual multiple core, thereby improving coding efficiency.
4. The method of claim 1 , wherein the step of obtaining the equivalent core comprises expanding seed data of the linear-feedback shift register LFSR to test data for improving coding efficiency.
5. The method of claim 4 , wherein the linear-feedback shift register LFSR simultaneously feeds the expanded seed to the multiple cores.
6. The method of claim 1 , wherein the step of obtaining the equivalent core comprises space multiplexing the multiple cores.
7. The method of claim 1 , wherein if the user-defined parameter number of tester channels are used no shadow register is needed to store seeds for the LFSR thereby minimizing overall test application time for the equivalent core.
8. The method of claim 1 , wherein if fewer than the user-defined parameter number of tester channels are used a scan clock for testing the equivalent core can be disabled until a new seed is completely transferred from the LFSR to the multiple cores.
9. A System-on-Chip test apparatus comprising:
a linear-feedback shift register LFSR;
a phase shifter with input coupled to output of the LFSR;
at least two intellectual property cores in parallel, and
an internal test access mechanism TAM interposed between the phase shifter and the cores;
wherein an equivalent core of the multiple cores is obtained and test data to the equivalent core is compressed from reseeding by the linear-feedback shift register, each core having a separate control signal enabling the respective core for its scheduled test interval.
10. The apparatus of claim 9 , wherein the at least two cores are tested in parallel such that testing time and encoding efficiency can be optimized simultaneously.
11. The apparatus of claim 9 , wherein the equivalent core has more care bits per slice scan than for any of the at least two cores.
12. The apparatus of claim 9 , wherein the equivalent core has a care-bit distribution over scan slices which is more flat than for any of the at least two cores, thereby improving coding efficiency.
13. The apparatus of claim 9 , wherein the equivalent core is obtained by expanding seed data of the linear-feedback shift register LFSR to test data for improving coding efficiency.
14. The apparatus of claim 13 , wherein the linear-feedback shift register LFSR simultaneously feeds the expanded seed to the at least two cores.
15. The apparatus of claim 9 , wherein the equivalent core is obtained by space multiplexing the at least two cores.
16. The apparatus of claim 9 , wherein testing time of the equivalent core is optimized by ensuring that for any scan slice of the equivalent core, the number of care bits does not exceed a user defined parameter such that the LFSR can guarantee to encode at least one scan slice.
17. The apparatus of claim 16 , wherein if the user-defined parameter number of tester channels are used no shadow register is needed to store seeds for the LFSR thereby minimizing overall test application time for the equivalent core.
18. The apparatus of claim 16 , wherein if fewer than the user-defined parameter number of tester channels are used a scan clock for testing the equivalent core can be disabled until a new seed is completely transferred from the LFSR to the multiple cores.