Method of manufacturing thin film transistor array panel
View Patent ↗A method of manufacturing a thin film transistor array panel includes forming an amorphous silicon film on an insulating substrate; forming a sacrificial film having an embossed surface on the amorphous silicon film; contacting a metal plate with the sacrificial film and performing heat-treatment for crystallizing the amorphous silicon film to change the amorphous silicon film to a polycrystalline silicon film; removing the metal plate and the sacrificial film; patterning the polycrystalline silicon film to form a semiconductor; forming a gate insulating layer which covers the semiconductor; forming a gate line on the gate insulating layer, a portion of the gate line overlapping the semiconductor; heavily doping a conductive impurity into portions of the semiconductor to form a source region and a drain region; forming an interlayer insulating layer which covers the gate line and the semiconductor; and forming a data line and an output electrode connected to the source and drain regions, respectively, on the interlayer insulating layer.
1. A method of manufacturing a thin film transistor array panel, the method comprising:
forming an amorphous silicon film on an insulating substrate;
forming a sacrificial film on the amorphous silicon film;
etching the sacrificial film to form embossing patterns;
contacting a metal plate with the sacrificial film after forming the embossing patterns;
performing heat-treatment to change the amorphous silicon film to a polycrystalline silicon film.
2. A method of manufacturing a thin film transistor array panel, the method comprising:
forming an amorphous silicon film on an insulating substrate;
forming a sacrificial film on the amorphous silicon film;
etching the sacrificial film to form embossing patterns;
contacting a metal plate with the sacrificial film;
performing heat-treatment to change the amorphous silicon film to a polycrystalline silicon film;
removing the metal plate;
removing the sacrificial film after removing the metal plate.
3. A method of manufacturing a thin film transistor array panel, the method comprising:
forming an amorphous silicon film on an insulating substrate;
forming a sacrificial film having a uniform embossed surface on the amorphous silicon film;
contacting a metal plate with the sacrificial film having the uniform embossed surface and performing heat-treatment for crystallizing the amorphous silicon film to change the amorphous silicon film to a polycrystalline silicon film;
removing the metal plate and the sacrificial film;
patterning the polycrystalline silicon film to form a semiconductor;
forming a gate insulating layer which covers the semiconductor;
forming a gate line on the gate insulating layer, a portion of the gate line overlapping the semiconductor;
heavily doping a conductive impurity into portions of the semiconductor to form at least one of a source region and drain region;
forming an interlayer insulating layer which covers the gate line and the semiconductor; and
forming a data line and an output electrode connected to the source and drain regions, respectively, on the interlayer insulating layer.
4. The method of claim 1 , further comprising:
removing the metal plate;
removing the sacrificial film after removing the metal plate.
5. The method of claim 1 ,
wherein the embossing patterns are arranged uniform.
6. The method of claim 1 , further comprising:
patterning the polycrystalline silicon film to form island patterns;
forming a gate line on the insulating substrate;
forming extrinsic region in parts of the island patterns by introducing impurities;
forming an insulating layer between the gate line and the island pattern;
forming an interlayer insulating layer which covers the gate line and the island pattern.
7. The method of claim 4 , further comprising:
patterning the polycrystalline silicon film to form a semiconductor;
forming a gate insulating layer which covers the semiconductor;
forming a gate line on the gate insulating layer, a portion of the gate line overlapping the semiconductor;
heavily doping a conductive impurity into portions of the semiconductor to form at least one of a source region and drain region;
forming an interlayer insulating layer which covers the gate line and the semiconductor; and
forming a data line and an output electrode connected to the source and drain regions, respectively, on the interlayer insulating layer.
8. The method of claim 2 , further comprising:
patterning the polycrystalline silicon film to form a semiconductor;
forming a gate insulating layer which covers the semiconductor;
forming a gate line on the gate insulating layer, a portion of the gate line overlapping the semiconductor;
heavily doping a conductive impurity into portions of the semiconductor to form at least one of a source region and drain region;
forming an interlayer insulating layer which covers the gate line and the semiconductor; and
forming a data line and an output electrode connected to the source and drain regions, respectively, on the interlayer insulating layer.
9. The method of claim 2 , wherein the step contacting the metal plate with the sacrificial film is performed after the step etching the sacrificial film to form the embossing patterns.
10. The method of claim 9 , wherein the embossing patterns are arranged uniform.
11. The method of claim 9 ,
wherein the embossing patterns are arranged uniform.
12. The method of claim 3 , wherein the embossed surface has protrusions and depressions which are regularly formed.
13. The method of claim 3 , wherein the sacrificial film has a thickness of about several tens to about several thousands of angstroms.
14. The method of claim 3 , wherein the sacrificial film is made of one of SiON, SiO 2 and SiNx.
15. The method of claim 3 , wherein the metal plate is a nickel plate.
16. The method of claim 3 , wherein metal plate contacts a raised portion of the embossed surface.